EET 365: Digital Logic and
Circuit Design
ECET 365:
Digital Logic and Circuit Design, Fall of 2005
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Tuesdays |
1:00 - 2:25 |
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Thursdays |
10:00 11:25 |
Tuesday 2:30 3:30, 4:00 5:45 (by appointment only)
Thursday 1:00 - 2:25
973-596-3000 (Day classes by 6 A.M., evening classes by 2 P.M.)
Course Objectives
By the end of the course you should be able to do the following:
·
Combinational
Logic. Analyze and design basic combinational logic systems. Develop,
simplify and implement (with various types of gates) sum of products (SOP) and
product of sums (POS) expressions. Analyze and design decoder logic including memory
systems for microcomputers. Analyze and design logic using multiplexers
including their use in time division multiplexing systems. Distinguish between
the various programmable logic devices and draw logic using the short hand
logic commonly used in PLDs.
·
Sequential
Logic. Analyze and design basic
sequential logic systems. Analyze various circuits, including determination of
waveforms and state diagrams, with SR, D, JK and T flip-flops. Design and
analyze various counters made up of the four types or flip-flops or using
universal counters. Design state machines in an efficient manner.
·
Software.
Simulate and trouble shoot simulations of the types of logic studied in the
course. Use the VHDL language to design, simulate and troubleshoot both combinational
and sequential logic using the CAD software. Present the results in a
well-documented report with all logic and timing diagrams computer generated.
·
Professionalism, Professional Societies and
Lifelong Learning. Appreciate the value of professionalism in your class
work, projects and career as well as the usefulness of, and role of
professional societies in, lifelong learning.
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Grading |
Homework |
10 % |
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Tests |
20 % |
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Projects |
35 % |
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Final Exam |
25 % |
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Professional Society Meeting attendance |
4 % |
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Technical Journal Report |
4 % |
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Library Research Project |
4 % |
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ECET 365:
Digital Logic and Circuit Design
Text: Brown and Vranesic, Fundamentals
of Digital Logic with VHDL Design, 2nd Ed., McGraw-Hill.
Software: Quartus II (included with
text)
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Week |
Date |
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Topics & Activities |
Homework & Project due dates |
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1 |
9/1 |
2.1 - 2.6 |
Introduction to
Combinational Logic, Boolean Algebra, Gates,
Logic Diagrams |
#1 |
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2 |
9/6, 8 |
2.7 -2.12 3.1 - 3.3 |
NAND & NOR
implementations, Introduction to
multiplexers, Introduction to CAD tools
and VHDL, NMOS and CMOS gates |
#2 Ch. 3: 1, 2, 3 |
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3 |
9/13, 15 |
4.1 - 4.5 |
Simplification of
Expressions, Truth Tables, K-maps, Dont cares,
Multi-output synthesis and analysis |
#3 |
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4, 5 |
9/20, 22 9/27, 29 |
3.9 6.1 - 6.4 6.6 - 6.8 |
Transmission Gates,
Decoders, Encoders, Multiplexers, VHDL for Combinational
Circuits |
#4 Project 1 due |
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6 |
10/4, 6 |
3.8 Notes |
Electrical Considerations Decoders and Memory Design Multi-level logic |
Instructor Assigned Problems |
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7 |
10/11, 13 |
5.1 - 5.3, 5.5 6.5, 9.6 |
Arithmetic Logic,
Comparators Hazards and Glitches |
#5 Ch.
6: 19, 20, 24 Ch.
9: 10, 12 Project 2 due |
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8 |
10/18, 20 |
3.6, 3.10 Notes |
ROMs & PROMs Programmable Logic Devices |
#6 |
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9 |
10/25, 27 |
7.1 - 7.7 |
Introduction to Sequential
Logic Latches and Flip Flops |
#7 |
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10 |
11/1, 3 |
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Latches and Flip Flops
Continued |
#8 Project 3 due. |
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11 |
11/8, 10 |
7.8 - 7.12 |
Registers & Counters,
VHDL & CAD tools |
#9 |
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12 |
11/15, 17 |
8.9 |
Analysis of Sequential
Logic State, Transition, and
Excitation Tables State Diagrams |
#10 |
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13,14 |
11/22,29 12/6, 8 |
8.1 - 8.7 |
Design of Sequential
Logic: Counters, Universal Counters, Sequence Detectors, State Reduction,
Binary Assignment, Excitation Equations |
#11 Project 4 due. |
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Outcome
# 1. Students will have the ability to analyze and design basic combinational
logic circuits. |
|||
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Strategies & Actions |
TAC Criterion 2 |
Program Outcomes |
Assessment Methods |
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Fundamentals
of combinational logic are covered in lectures, homework, and projects 1 - 3.
In teams, students use the software, write reports, and participate in class
exercises. |
a
g, k |
1,2,3,4,7,
8 |
Tests,
Homework, and reports of the projects are graded. |
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Outcome
# 2. Students will have the ability to analyze and design basic sequential
logic circuits. |
|||
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Strategies & Actions |
TAC Criterion 2 |
Program Outcomes |
Assessment Methods |
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Fundamentals
of sequential logic are covered in lectures, homework, and project 4. In
teams, students use the software, write reports, and participate in class
exercises. |
a
g, k |
1,2,3,4,7,8 |
Tests,
Homework, and reports of the projects are graded. |
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Outcome
# 3. Students
will have the ability to simulate and troubleshoot simulations of
combinational and sequential logic. They will be able to create designs using
vhdl. |
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Strategies & Actions |
TAC Criterion 2 |
Program Outcomes |
Assessment Methods |
|
Fundamentals
of the software are covered in lectures, homework, and project 4. In teams,
students use the software, write reports, and participate in class exercises. |
a
g, k |
1,2,3,4,7,8 |
Tests,
Homework, and reports of the projects are graded. |
|
Outcome
# 4. Students will appreciate the value of professionalism and timeliness in
their class work, projects and career as well as the usefulness of, and role
of professional societies in, lifelong learning. |
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Strategies & Actions |
TAC Criterion 2 |
Program Outcomes |
Assessment Methods |
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Homework
and project reports are on a strict schedule and must follow professional
standards in their content and structure. Students are required to submit a
brief report on their attendance at a professional society meeting and a
brief report from a technical journal article. |
g,
h, i, k |
3,
5, 6,8 |
Reports
graded. |
TAC of ABET
stands for the Technology Accreditation Commission of ABET,
Homework: Students are expected to do all homework as specified in the syllabus. Homework will be collected. In regard to doing the homework, please keep in mind the Chinese proverb: " I hear and forget, I see and remember, I do and I understand."
Projects: Four projects will be assigned, valued at 5, 10, 10 and 10 points for a total of 35 % of the final grade. The students are expected to learn the software. It is strongly urged that students start learning the software immediately by reading the manual and trying the practice examples in the manual. The projects are to be done by the students in groups of two, submitting one report per group alternating who writes the report. Projects may NOT be submitted via email.
Project Documentation Requirements:
· Pages numbered
· Table of Contents
· Introduction, or abstract, Discussion (integrated into report), and Conclusion
· Everything clearly labeled
· All truth tables and Karnaugh maps (preferably typed)
· Clear, hand-written check (in pencil) on computer printouts of the simulation
· Schematics and timing diagrams printed from the computer
· Timing diagrams printed logically - inputs on top, outputs beneath the inputs (any waveforms not labeled are useless!)
Tests and Exams : All quizzes and exams will be closed book. There will be several quizzes (the lowest quiz grade will be dropped) during the semester and a final exam.
Missed Tests: Only one makeup test will be given, it will be fair but challenging. Missing the final exam without a valid excuse results in a zero.
Note: all students
enrolled in the class will receive the above material as well as other
information (course notes) in a document to be distributed the first day of
class.