Phys 728, Spring 2003
Homework Problem Set #7
7.1 We discussed in class the idea that one could take an IF signal
of bandwidth B, digitize it, and send it into a "time-demultiplexer" that
can then feed into a lag correlator operating at a slower clock rate.
The example we used in class was to digitize at 1 GHz, then use an 8-bit
shift register to time-demultiplex by a factor of 8, to get down to a clock
speed of 1 GHz / 8 = 125 MHz. Refer to these
pages of a pdf file that describes correlator design. The first
page gives definitions of the symbols used on the second page, which is
a list of steps to design a correlator. These steps tell how to design
a time-demultiplexing correlator, and a "deep memory" correlator.
Please disregard the latter instructions, and answer the following about
the design parameters for a time-demultiplexing correlator with the following
parameters:
-
bandwidth B = 300 MHz,
-
required spectral resolution Df
= 3 MHz
-
lag correlator clock speed 100 MHz
-
correlator chips with number of lags NC = 8.
(a) What must be the digitizer clock speed in order to digitize at
the Nyquist rate?
(b) What is the required number of lags, NR?
(c) How many bits must the time-demultiplexer (shift register) have?
(This is D in the write-up.)
(d) What is the basic number of correlator chips needed? (This
is NB in the write-up.)
(e) What is the number of independent lags available per chip?
(f) How many chips must be cascaded (i.e. used in series)?
(g) What is the actual frequency resolution Df
we will get with this design?
7.2 You should have gotten that the actual frequency resolution above
was Df = 2.5 MHz, which is
better than desired. Thus, there is some waste of capacity in this
design. Let's say that the actual time-demultiplexer is 8-bits, and
we can make our digitizer any speed we want. What speed of digitizer
(near 1 GHz) would give us 3 MHz spectral resolution, so that there would
be no waste of capacity? What is the corresponding bandwidth?
Note that you will have to choose a bandwidth such that the number of cascaded
chips (NCC) is an integer.