Quote: A Smith & Wesson beats four aces.
(Courtesy of fortune cookies)

Welcome to the Cool Spot of the Sun

Niagara The Superefficient chip?

        Niagara from SUN, might not be the most expected chip around. Reason, RISC machine being dominated over by the pseudo RISC, high frequency beast(x86 is the main factor though) like the Opteron and the Xeon. So what makes Niagara so special. Is it the targeted 1-1.2Ghz speed or the 8 cores. The speed has been a sore point for Microprocessor companies. Specially the 4.0Ghz debacle for Intel, when back in 2001, it predicted to reach 10Ghz in a few years. So much for the NetBurst technology which went burst before it even reached 4.0ghz. The most cored commercial system today other than SUN's is the Power 5 family. These beasts are magnificient, as they feature multi-cores with a stupendous inter-core connections that put to shame even HyperTransport(tm).

          I first read about Niagara back in the days when the company which made niagara was acquired by SUN.
I read an article on Dr.Kunle of Stanford who was a major architect on it. The most interesting thing on Niagara was the way it made sure each and every functional unit was utilized the maximum by the program. With 8 cores and 4 threads per core, with a theoritical maximum of 32 threads running in parallel, its a magnificient threaded beast. What makes it more interesting is its thread utilization is almost 100% which can't be said of contemporary microprocessor. It features extensive network enhanced hardware modules.

         According to me what makes Niagara as interesting as CELL is its revolutionary way to make chips faster for computing, and leaving behind clock speed as the most major way to increase efficiency or better performance. Niagara's each core has a pipeline depth of 6, which is quite small considering the standard core pipeline depth of 32 for P4 or the Preshot(aka Intel Prescott) or the supposedly 12 Pipeline stages of a Pentium M(I am too lazy to look that up, but yup its very less compared to P4). The main reason i suppose why P4 need high speed to get good performance is a deeper pipepline implies faster performance bar high misses. Unless P4 reaches a theoritical 6Ghz speed, the pipeline misses are more than what it can afford. By the way for a nice guide on threading, pipelining see here.

          The most efficient IPC currently is of Pentium M followed by either Athlon64 and/or the PowerPC. Problem is i forgot where i got the info from, but i forgot it. If you know the place where IPC(instructions per Cycle) comparison is done Vs the processor architecture, please please drop me a mail here at abhishek@ieee.org . The reason I remember this titbit information is because i hate to see my favourite architechture K8(AMD64) lose against Pentium-M(P3 derivatives). Good gosh, the engineers in Israel have done a wonderful task with the Pentium -M. And the reason I mention this is good chips with high performance can be achieved by low pipeline depth processors(Pentium-M) and massively threaded(CELL and Niagara). There is always room at the bottom. To me Pentium-4 represents the other end of the spectrum, which has not yet dawned on us, as we would need new technologies to reach 10Ghz to understand the real possibilities of that other end of spectrum.

         Anyways other than speculation, till date, today as of in November'05, few facts on Niagara is known, like its core capabilities and its targeted audience of web-servers. SUN is going to unveil in december'05, UltraSparc T1 based on Niagara. And this is probably where everyone should look for more information. By the way a prelimnary design of the Niagara processor was explained in the IEEE Spectrum magazine. Dr Kunle does have a link to that here . More on Niagara would be posted as more info comes. Wish I had a simulator to simulate Niagara's working like with CELL.

Update: Niagara Released!
Known to power T1000 and T2000 systems and their comparisons . Also known is the fact that there is just 1 FPU per chip, Niagara 2 will be having 1 per core and with 8 threads/core, with a total of 64 threads/chip. Drool! I bet niagara is very good for web computation.