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	Jie Hu Assistant Professor Dept. of Electrical and Computer Engineering New Jersey Institute of Technology Ph.D. The Pennsylvania State University - UP M.E. Peking University B.E. Beijing University of Aeronautics & Astronautics
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Prof. Hu received his Ph.D. degree in Computer Science and Engineering from the Pennsylvania State University in 2004. Before that, he received his B.E. degree in Computer Science and Engineering from Beijing University of Aeronautics and Astronautics, China, in 1997, and his M.E. degree in Signal and Information Processing from Peking University, China, in 2000. He joined the Electrical and Computer Engineering Department at New Jersey Institute of Technology as an Assistant Professor in 2004.
Research Interests: Computer Architecture, Compiler Optimization, and VLSI Deisgn. Group: Computer Architecture and Parallel Processing Laboratory (CAPPL) Projects: Reliable Processor Architectures against Soft Errors, Thermal-aware Microarchitecture, Low Power Processor Micro-/Architecture, Reconfigurable Computing, Networks-on-Chip (NoCs).
Selected Publications (complete list of publications) Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. Accepted for publication in IEEE Transactions on Computers (TC), 2009. Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 27, No. 8, pp. 1503-1507,2008. S. Wang, H. Yang, J. Hu, and S. G. Ziavras. Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance. In Microprocessors and Microsystems, Volume32, Issue 3, pp. 171 - 182, May 2008. J. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Analyzing Data Reuse for Cache Reconfiguration. In ACM Transactions on Embedded Computing Systems (TECS), Volume 4, No. 4, pp. 851 - 876, November 2005. Shuai Wang, Jie Hu, and Sotirios G. Ziavras. BTB Access Filtering: A Low Energy and High Performance Design. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81 - 86, Montpellier, France, April 7-9, 2008. (Nominated for Best Paper Award) Jie Hu, Shuai Wang and Sotirios G. Ziavras. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN-2006) - Dependable Computing and Communications Symposium (DCCS), pp. 281 - 290, Philadelphia, PA, June 25-28, 2006. Johnsy K. John, Jie S. Hu, and Sotirios G. Ziavras. Optimizing the Thermal Behavior of Subarrayed Data Caches. In Proc. of IEEE International Conference of Computer Design (ICCD-2005), pp. 625 - 630, San Jose, California, October 2-5, 2005.
Teaching ECE252 - Microprocessors ECE251 - Digital Design ECE692 - Embedded Computing Systems ECE690 - Computer Systems Architecture ECE789 - Advanced Topics in Computer Architecture
Students Current students: Shuai Wang (Ph.D.) Parijat Shukla (M.S.) Alumni: Johnsy K. John (Ph.D.) now at AMD Yuncong Zhang, MS, Exploiting Narrow-Width Value for VLIW Register File Designs, Fall 2008 Chris Onjian, MS, Case Studies of Design and Implementation Issues Resulting in Data Integrity Problems in Real Time Embedded Systems, Spring 2008 Gobinder Waraich, MS, Digital Alarm Clock with Temperature Display, Fall 2007 Ying Zhu, MS, Adopting Freescale PBMCUSLK/AP52233SLK for Educational Projects, Fall 2007 Carla Nunez, MS, Power-/Complexity-Effective Register Files in SMT Processors, May 2007 Michael Kramarczyk, MS, A System Approach for Designing and Implementing TTDL, Fall 2006 Sree Lakshmi, MS, Improving Data Cache Performance and Power Efficiency via Store Buffering, 2005 Farhan Javed, Senior Project, Sensor Network Communication, Spring 2007 Muzaffar Zaman, Senior Project, Sensor Network Communication, Spring 2007 Gian Francisco, Senior Project, ASIC Encoder with an Integrated Look-up Table (2nd Place Winner), Spring 2007 Swati Jani, Senior Project, ASIC Encoder with an Integrated Look-up Table (2nd Place Winner), Spring 2007 Akinola Akiwowo, Senior Project, ASIC Encoder with an Integrated Look-up Table (2nd Place Winner), Spring 2007 Joannie Bautista, Senior Project, Power-Aware Register File Designs, 2006 Luis Salinas, Senior Project, Power-Aware Register File Designs, 2006 Waqas Mahmood, Senior Project, Leakage Behavior of SRAM Memory and Its Optimizations, 2005 Tim Hutchins,Senior Project, Leakage Behavior of SRAM Memory and Its Optimizations, 2005
Contact 331 Electrical & Computer Engineering Center University Heights Newark, NJ 07102 Email: jhu AT njit dot edu Tel: (973)596-5273 Fax: (973)596-5680