Jie Hu, Shuai Wang, and Sotirios G. Ziavras. On the Exploitation of Narrow-Width Values for Improving Register File Reliability. Accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2008.
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability. Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2008.
S. Wang, H. Yang, J. Hu, and S. G. Ziavras. Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance. In Microprocessors and Microsystems, Volume32, Issue 3, pp. 171 - 182, May 2008. (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. BTB Access Filtering: A Low Energy and High Performance Design. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81 - 86, Montpellier, France, April 7-9, 2008. (PS.gz, PS, PDF) (accepted 74 out of 245 submissions, acceptance rate: 30%) (Nominated for Best Paper Award)
2007
Hongyan Yang, Sotirios G. Ziavras, and Jie Hu. Reconfiguration Support for Vector Operations. In International Journal of High Performance Systems Architecture (IJHPSA), Volume 1, No. 2, pp. 89 - 97, 2007. (PDF)
J. Hu, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir. Optimizing Power Efficiency in Trace Cache Fetch Unit. In IET Computers & Digital Techniques, Volume 1, Issue 4, pp. 334 - 348, July 2007. (PDF)
Xiaofang Wang, Sotirios G. Ziavras, and Jie Hu. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. In Proc. of the 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), pp. 61 - 70, Las Vegas, Nevada, June 25-28, 2007. (PDF)
S. Wang, H. Yang, J. Hu, and S. Ziavras. Asymmetrically Banked Value-Aware Register Files. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 363 - 368, Porto Alegre, Brazil, May 9-11, 2007. (PS.gz, PS, PDF) (accepted 66 out of 174 submissions, acceptance rate: 38%)
H. Yang, S. Wang, S. Ziavras, and J. Hu. Vector Processing Support for FPGA-Oriented High Performance Applications. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 447 - 448, Porto Alegre, Brazil, May 9-11, 2007. (PS.gz, PS, PDF) (Poster, accepted 27 out of 174 submissions)
Hongyan Yang, Sotirios Ziavras and Jie Hu. FPGA-based Vector Processing for Matrix Operations. In Proc. of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), Las Vegas, Nevada, April 2-4, 2007. (PDF)
2006
J. S. Hu, G. Chen, M. Kandemir and N. Vijaykrishnan. Software Power Optimzation. Book Chapter in System on Chip: Next Generation Electronics, pp. 289 - 316, edited by Bashir M. Al-Hashimi, IEE Press, ISBN: 0-86341-552-0 & 978-086341-552-4.
J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Compiler-Assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems. Accepted for publication in ACM Transactions on Embedded Computing Systems (TECS), 2006.
X. Wang, S. G. Ziavras, and J. Hu. System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. IEEE International Conference on Computer Design (ICCD2006), San Jose, CA, Oct. 1-4, 2006. (PS.gz, PS, PDF) (accepted 72 out of 231 submissions, acceptance rate: 31%)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. In Proc. of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 14 - 20, Samos, Greece, July 17-20, 2006. (PS.gz, PS, PDF) (accepted 26 (for IC-SAMOS) out of 130 submissions, acceptance rate: 20%)
Jie Hu, Shuai Wang and Sotirios G. Ziavras. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN-2006) - Dependable Computing and Communications Symposium (DCCS), pp. 281 - 290, Philadelphia, PA, June 25-28, 2006. (PS.gz, PS, PDF) (accepted 34 out of 187 submissions, acceptance rate: 18%)
2005
J. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Analyzing Data Reuse for Cache Reconfiguration. In ACM Transactions on Embedded Computing Systems (TECS), Volume 4, No. 4, pp. 851 - 876, November 2005. (PDF)
J. S. Hu, G. M. Link, J. K. John, S. Wang, and S. G. Ziavras. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. In Proc. of Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), Springer Verlag LNCS 3740, pp. 200 - 214, Singapore, October 24-26, 2005. (PS.gz, PS, PDF)
Johnsy K. John, Jie S. Hu, and Sotirios G. Ziavras. Optimizing the Thermal Behavior of Subarrayed Data Caches. In Proc. of IEEE International Conference of Computer Design (ICCD-2005), pp. 625 - 630, San Jose, California, October 2-5, 2005. (PS.gz, PS, PDF) (accepted 101 out of 313 submissions, acceptance rate: 32%)
J. S. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-Directed Instruction Duplication for Soft Error Detection. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'05), pp. 1056 - 1057, Munich, Germany, March 7-11, 2005. (PS.gz, PS, PDF) (accepted 65 out of 173 submissions, acceptance rate: 37.5%)
2004
W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy. In ACM Transactions on Architecture and Code Optimization (TACO), Volume 1, No. 1, pp. 3 - 33, March 2004.(PDF)
J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, and M. J. Irwin. Scheduling Reusable Instructions for Power Reduction. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'04), pp. 148 - 153, Paris, France, February 16-20, 2004. (PS.gz, PS, PDF) (accepted 181 out of 780 submissions, acceptance rate: 23%)
Jie S. Hu, N. Vijaykrishnan, and Mary Jane Irwin. Exploring Wakeup-Free Instruction Scheduling. In Proc. of the International Symposium on High Performance Computer Architecture (HPCA-10), pp. 232 - 241, Madrid, Spain, February 14-18, 2004. (PS.gz, PS, PDF) (accepted 27 out of 151 submissions, acceptance rate: 18%)
N. Vijaykrishnan and Jie S. Hu. Designing Energy Aware Systems. In MRTC (Malardalen Real-Time Research Centre) Report, pp. 12 - 15. ISSN 1404-3041, ISRN MDH-119/2004-1-SE, 2004. Invited Paper. (PS, PDF)
2003
N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and N. Vijaykrishnan. Leakage Current: Moore's Law Meets Static Power. In IEEE Computer Special Issue on Power- and Temperature-Aware Computing, pp. 68 - 75, December, 2003. (PDF)
J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 402 - 407, Seoul, Korea, August 25-27, 2003. (PS.gz, PS, PDF) (accepted 54 out of 221 submissions, acceptance rate: 24%)
J. S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. In Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), pp. 127 - 132, Tampa, Florida, February 20-21, 2003. (PS.gz, PS, PDF) (accepted 26 out of 115 submissions, acceptance rate: 23%)
2002
W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-Directed Instruction Cache Leakage Optimization. In Proc. of the 35th Annual International Symposium on Microarchitecture (MICRO-35), pp. 208 - 218, Istanbul, Turkey, November 18-22, 2002. (PS.gz, PS, PDF) (accepted 36 out of 150 submissions, acceptance rate: 24%)
J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, and W. Zhang. Compiler-Directed Cache Polymorphism. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 165 - 174, Berlin , Germany , June 19-21, 2002. (PS.gz, PS, PDF) (accepted 25 out of 73 submissions, acceptance rate: 34%)
H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, and U. Kremer. Energy-Conscious Compilation Based on Voltage Scaling. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 2 - 11, Berlin , Germany , June 19-21, 2002. (PS.gz, PS, PDF) (accepted 25 out of 73 submissions, acceptance rate: 34%)
J. S. Hu, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Power-Efficient Trace Caches. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'02), p. 1091 (Poster), Paris, France, 4-8 March, 2002. (accepted 210 out of 476 submissions, acceptance rate: 44%)