Research

Professor Jie Hu’s research interests are in the areas of computer architecture, power-aware systems design, power-efficient reliable systems, compiler optimizations for performance and power consumption, VLSI design, and reconfigurable computing architecture. The following projects outline his research efforts on designing high-performance, low-power, and reliable systems at new technology generations.
 

Processor Reliability against Soft Errors

Along with dramatic performance improvements driven by advancing silicon technologies, future microprocessors are becoming even more vulnerable to soft errors induced by energetic particle strikes such as alpha particles (emitted by decaying radioactive impurities in packaging and interconnect materials) and high-energy neutrons induced by cosmic rays. Thus, designing new generation microprocessors against soft errors has arisen as a major requirement along with performance and power considerations.

His research has targeted at on-chip components that dominate the transistor budget and die area, such as register files and caches, as well as the processor datapath, suffering from an increased exposure to high-energy particle strikes. He has proposed in this research to exploit dynamic resource usage in the datapath pipeline, value-aware computing, cache memory lifetime and vulnerability behavior, compiler assisted instruction duplication and scheduling, and transactional processor architecture for cost-effective reliable computing under various performance, power/energy, thermal, cost/area/size constraints. His work has led to one of the very first hybrid (software-hardware) reliable schemes, a highly cost-effective reliable IRD register file design, the very first self-adaptive reliable data cache microarchitecture, and a new methodology for deriving implicit reliable schemes for on-chip caches based on their lifetime and soft-error vulnerability characterization. 

Project Sponsors

Publications

  • Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. In IEEE Transactions on Computers (TC), Volume 58, No. 9, pp. 1171 - 1184, September 2009. (PDF)
  • J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Compiler-Assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems. In ACM Transactions on Embedded Computing Systems (TECS), Volume 8, No. 4, Article 27, July 2009. (PDF)
  • Jie Hu, Shuai Wang, and Sotirios G. Ziavras. On the Exploitation of Narrow-Width Values for Improving Register File Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Volume 17, No. 7, pp. 953 - 963. July 2009. (PDF)
  • Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 27, No. 8, pp. 1503 - 1507, August 2008. (PDF)
  • Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. In Proc. of the 6th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2006), pp. 14 - 20, Samos, Greece, July 17-20, 2006. (PS.gz, PS, PDF) (accepted 26 (for IC-SAMOS) out of 130 submissions, acceptance rate: 20%)
  • Jie Hu, Shuai Wang and Sotirios G. Ziavras. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN-2006) - Dependable Computing and Communications Symposium (DCCS), pp. 281 - 290, Philadelphia, PA, June 25-28, 2006. (PS.gz, PS, PDF) (accepted 34 out of 187 submissions, acceptance rate: 18%)
  • J. S. Hu, G. M. Link, J. K. John, S. Wang, and S. G. Ziavras. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. In Proc. of Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), Springer Verlag LNCS 3740, pp. 200 - 214, Singapore, October 24-26, 2005. (PS.gz, PS, PDF)
  • J. S. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-Directed Instruction Duplication for Soft Error Detection. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'05), pp. 1056 - 1057, Munich, Germany, March 7-11, 2005. (PS.gz, PS, PDF) (accepted 65 out of 173 submissions, acceptance rate: 37.5%)

Processor Thermal Control/Security

As technology trends are packing transistors even more tightly, the on-chip power densities are exponentially increasing. In addition, slow supply voltage scaling further deteriorates this situation. Power densities have become high enough to cause serious thermal challenges, possibly even resulting in a project cancellation. This in turn leads to demands for much larger cooling capacity in the microprocessor designs, thus significantly increasing the costs of cooling systems and chip packaging. Without proper consideration of thermal problems, permanent damage (thermal runaway) or gradual damage (accelerated aging) on the microprocessor would be suffered.

This research proposes to study the fine-grain thermal behavior of subarrays within the data cache, to gain insight in microarchitectural optimizations for on-chip caches. This study has led to a new thermal-aware cache microachitecture, the way-interleaved subarrayed cache (-il) that employs cache way distribution among subarrays and the subblock predecoding to reduce the dynamic power consumption and subarray temperatures, as shown in Figure 1. This research has also suggested that a joint effort from both microarchitectural designs and dynamic schemes such as dynamic thermal management (DTM) for power optimizations is required to improve the efficiency of thermal management.

Figure 1. Effectiveness of Thermal Aware Cache Microarchitecture

As conventional DTM techniques allocate thermal sensors to potential on-chip hotspots such as integer register file and functional units to monitor chip-wide temperature at runtime and dynamically invoke power reduction schemes to avoid thermal emergency. The deficiency in this design philosophy can be exploited by malicious software to create hotspots in un-monitored structures for thermal attack. This research, for the first time, introduces the concept of thermal attacks on unexpected fine-grain hotspots, demonstrates how fine-grain localized hotspots threaten the thermal reliability that can not be protected by existing thermal sensors, and provides effective protection solutions. Figure 2 shows that the proposed protection scheme successfully defends the thermal attack on the instruction cache. The outcome of this research will enable future generation microprocessor to continue increasing their computing power under the thermal budget as well as defending the thermal virus. 

Figure 2. Protecting Inst. Cache from Thermal Attack

Publications

  • J. Kong, J. K. John, E-Y. Chung, S. W. Chung, and J. Hu. On the Thermal Attack in Instruction Caches. Accepted for publication in IEEE Transactions on Dependable and Secure Computing (TDSC), 2009.

  • S. Wang, J. Hu, S. G. Ziavras, and S. W. Chung. Exploiting Narrow-Width Values for Thermal-Aware Register File Designs. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'09), pp. 1422 - 1427, Nice, France, April 20-24, 2009. (PS.gz, PS, PDF) (accepted 226 out of 965 submissions, acceptance rate: 23%)

  • Jie Hu, Johnsy K. John, and Shuai Wang. Thermal-Aware Subarrayed Data Cache Microarchitectures. In International Journal of Intelligent Control and Systems (IJICS), Volume 13, No. 4, pp. 251 – 263, December 2008.

  • Johnsy K. John, Jie S. Hu, and Sotirios G. Ziavras. Optimizing the Thermal Behavior of Subarrayed Data Caches. In Proc. of IEEE International Conference of Computer Design (ICCD-2005), pp. 625 - 630, San Jose, California, October 2-5, 2005. (PS.gz, PS, PDF) (accepted 101 out of 313 submissions, acceptance rate: 32%)
Low Power Systems Design

Excessive power consumption is widely considered as a major impediment to designing future microprocessors for applications ranging from small sensors to large computer servers. In small embedded and mobile systems, the limited battery capacity is the main concern since the battery technology improvements have not matched to the increasing power requirements of the computing resources. Power dissipation has become an important issue in desktop systems and server environments for a variety of other reasons. The increasing power density due to the miniaturization of the circuits makes the task of packaging and cooling harder and costlier. Higher power densities also translate to higher on-chip temperatures and make it
necessary to support costlier packaging. Power and cooling requirements are also a major bottleneck for many data centers and is considered a significant part of the operating cost. The higher power densities also degrade system reliability. Furthermore, the increasing current draw poses difficulties in the power supply grid design. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor’s power budget. Leakage is projected to account for 70% of the cache power budget in 70nm technology. This research explores and has developed new approaches to synergizing novel processor microarchitectures, compiler optimizations and techniques, program phase behavior characterization, and VLSI circuit techniques for holistic solutions to future low-power computing.

Publications

  • S. Wang, H. Yang, J. Hu, and S. G. Ziavras. Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance. In Microprocessors and Microsystems, Volume32, Issue 3, pp. 171 - 182, May 2008. (PDF)
  • Shuai Wang, Jie Hu, and Sotirios G. Ziavras. BTB Access Filtering: A Low Energy and High Performance Design. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81 - 86, Montpellier, France, April 7-9, 2008. (PS.gz, PS, PDF) (accepted 74 out of 245 submissions, acceptance rate: 30%) (Nominated for Best Paper Award)
  • J. Hu, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir. Optimizing Power Efficiency in Trace Cache Fetch Unit. In IET Computers & Digital Techniques, Volume 1, Issue 4, pp. 334 - 348, July 2007. (PDF)
  • S. Wang, H. Yang, J. Hu, and S. Ziavras. Asymmetrically Banked Value-Aware Register Files. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 363 - 368, Porto Alegre, Brazil, May 9-11, 2007. (PS.gz, PS, PDF) (accepted 66 out of 174 submissions, acceptance rate: 38%)
  • J. S. Hu, G. Chen, M. Kandemir and N. Vijaykrishnan. Software Power Optimzation. Book Chapter in System on Chip: Next Generation Electronics, pp. 289 - 316, edited by Bashir M. Al-Hashimi, IEE Press, ISBN: 0-86341-552-0 & 978-086341-552-4, 2006.
  • J. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Analyzing Data Reuse for Cache Reconfiguration. In ACM Transactions on Embedded Computing Systems (TECS), Volume 4, No. 4, pp. 851 - 876, November 2005. (PDF)
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy. In ACM Transactions on Architecture and Code Optimization (TACO), Volume 1, No. 1, pp. 3 - 33, March 2004.(PDF)
  • J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, and M. J. Irwin. Scheduling Reusable Instructions for Power Reduction. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'04), pp. 148 - 153, Paris, France, February 16-20, 2004. (PS.gz, PS, PDF) (accepted 181 out of 780 submissions, acceptance rate: 23%)
  • N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and N. Vijaykrishnan. Leakage Current: Moore's Law Meets Static Power. In IEEE Computer Special Issue on Power- and Temperature-Aware Computing, pp. 68 - 75, December, 2003. (PDF)
  • J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 402 - 407, Seoul, Korea, August 25-27, 2003. (PS.gz, PS, PDF) (accepted 54 out of 221 submissions, acceptance rate: 24%)
  • J. S. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. In Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), pp. 127 - 132, Tampa, Florida, February 20-21, 2003. (PS.gz, PS, PDF) (accepted 26 out of 115 submissions, acceptance rate: 23%)
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-Directed Instruction Cache Leakage Optimization. In Proc. of the 35th Annual International Symposium on Microarchitecture (MICRO-35), pp. 208 - 218, Istanbul, Turkey, November 18-22, 2002. (PS.gz, PS, PDF) (accepted 36 out of 150 submissions, acceptance rate: 24%)
  • J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, and W. Zhang. Compiler-Directed Cache Polymorphism. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 165 - 174, Berlin , Germany , June 19-21, 2002. (PS.gz, PS, PDF) (accepted 25 out of 73 submissions, acceptance rate: 34%)
  • H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, and U. Kremer. Energy-Conscious Compilation Based on Voltage Scaling. In Proc. of ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 2 - 11, Berlin , Germany , June 19-21, 2002. (PS.gz, PS, PDF) (accepted 25 out of 73 submissions, acceptance rate: 34%)
  • J. S. Hu, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Power-Efficient Trace Caches. In Proc. of the Conference on Design, Automation and Test in Europe (DATE'02), p. 1091 (Poster), Paris, France, 4-8 March, 2002. (accepted 210 out of 476 submissions, acceptance rate: 44%)
FPGA-based Reconfigurable Computing Architecture

Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-on-a-Programmable-Chip (MPoPCs) represent the recent trend in this arena, which integrate the advantages of both software
programmability and hardware reconfigurability, providing substantial flexibility that can result in programming ease and high performance. This research effort has lead to the development of powerful system-level tools and models to estimate and verify the energy consumption in the early design stages, targeting the HERA (HEterogeneous Reconfigurable Architecture), a versatile reconfigurable MPoPC that we have implemented on Xilinx FPGAs. We further explored an application-oriented design methodology that customizes HERA to match the diverse computation and communication characteristics of tasks in the application, under application specific energy-performance objectives. FPGA-based data-parallel high performance computing is another topic in this research.

Publications

  • Hongyan Yang, Sotirios G. Ziavras, and Jie Hu. Reconfiguration Support for Vector Operations. In International Journal of High Performance Systems Architecture (IJHPSA), Volume 1, No. 2, pp. 89 - 97, 2007. (PDF)
  • Xiaofang Wang, Sotirios G. Ziavras, and Jie Hu. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. In Proc. of the 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), pp. 61 - 70, Las Vegas, Nevada, June 25-28, 2007. (PDF)
  • H. Yang, S. Wang, S. Ziavras, and J. Hu. Vector Processing Support for FPGA-Oriented High Performance Applications. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 447 - 448, Porto Alegre, Brazil, May 9-11, 2007. (PS.gz, PS, PDF) (Poster, accepted 27 out of 174 submissions)
  • Hongyan Yang, Sotirios Ziavras and Jie Hu. FPGA-based Vector Processing for Matrix Operations. In Proc. of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), Las Vegas, Nevada, April 2-4, 2007. (PDF)
  • X. Wang, S. G. Ziavras, and J. Hu. System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. IEEE International Conference on Computer Design (ICCD2006), San Jose, CA, Oct. 1-4, 2006. (PS.gz, PS, PDF) (accepted 72 out of 231 submissions, acceptance rate: 31%)