Instructor: Jie Hu (jie.hu@njit.edu) Office: 331 ECEC
Office Hours: T 3:30PM – 5:00PM, F 3:30PM – 5:00PM Phone: (973)596-5273
Prerequisites: FED 101 and Phys 121.
Textbook: Introduction to Logic Design, by Alan B. Marcovitz, 2nd Edition, McGraw-Hill, ISBN 0-07-286516-4, 2005.
Lecture Notes: available for each class on the course website.
Class Meeting Time: R 5:45PM – 9:50PM Class Meeting Place: ECEC 100
Course Description: An introduction to the design of combinational and sequential logic circuits used in digital processing systems and computers. Basic register transfer operations are covered. Topics include Boolean algebra, minimization techniques and the design of logic circuits such as adders, comparators, decoders, multiplexers, counters, arithmetic logic units, and memory systems.
Course Objective: This course provides students with a basic understanding of digital device and circuit fundamentals. The students should be able to design and analyze both combinational and sequential circuits after completing this course.
Weekly Outline (subject to change):
|
Week |
Subject |
Reading |
|
1 |
Introduction to Digital Systems, Number Representations, Truth Table & Switching Algebra |
Ch. 1 |
|
2 |
Manipulation of Algebraic Functions, From Truth Table to Algebraic Expression, Introduction to Karnaugh Map (K-map) |
Ch. 2 pp. 46-73 |
|
3 |
Karnaugh Map (K-map), Simplification of Algebraic Expressions, |
Ch. 2, pp. 65-90 |
|
4 |
Manipulation of Algebraic Functions, The Karnaugh Map (K-map), Review for Midterm Exam #1 |
Ch. 2, Ch. 3, pp. 90-146 |
|
5 |
K-map with Don’t Cares, Midterm Exam #1 |
Ch. 3, pp. 146-156
|
|
6 |
Problem Solving for Exam #1, Five- and Six-Variable K-maps, Multiple Output Problems |
Ch. 3, pp. 156-174 |
|
7 |
Hazards and Glitches, Adders, Decoders, Multiplexers |
Ch. 5, pp. 262-281 |
|
8 |
Gate Arrays, Introduction to Sequential Systems, Latches and Flip-Flops |
Ch. 5, Ch. 6, pp. 282-376 |
|
9 |
Analysis of Sequential Systems, Designing Sequential Systems, Review for Midterm Exam #2 |
Ch. 6, pp. 376-386 |
|
10 |
Sequential Circuit Design with F/F, The Design of Counters, Midterm Exam #2 |
Ch. 7, pp. 414-443 |
|
11 |
Problem Solving for Exam #2, Derivation of State Tables and State Diagrams, Finite State Machines |
Ch. 7, pp. 443-457 |
|
12 |
Registers, Programmable Logic Devices (PLDs), |
Ch. 8, pp. 485-503 |
|
13 |
State Reduction Using Tabular Method, Partitions |
Ch. 9, pp. 535-549 |
|
14 |
State Reduction Using Partitions Final Review |
Ch. 9, pp. 549-560 |
Grading Policy: Grades will be determined by homework assignments (15%), pop quizzes/class participation (10%), two midterm exams (20% each), and one final exam (35%).
Academic Integrity
The NJIT Honor Code will be upheld and any violations will be brought to the
immediate attention of the Dean of Students.