Publications, Proceedings, Presentations, and Patents

 

Research Papers

Input Queued Packet Switches

                                                                                

 

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Nabeel Al-saber, Saurab Oberoi, Roberto Rojas-Cessa and Sotirios G. Ziavras, “Concatenating Packets for Variable-Length Input-Queue Packet Switches with Cell-Based and Packet-Based Scheduling,” accepted in IEEE Sarnoff Symposium, Princeton, NJ, April 28-30, 2008.

 

 

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Captured-Frame Matching Schemes for Scalable Input-Queued Packet Switches,” Computer Communications (Elsevier), Vol. 30, Issue 10, pp. 2149-2161, July 2007.

 

 

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Zhen Guo and Roberto Rojas-Cessa, “A Control Theoretic Analysis of Arbitration and Matching Schemes for Input Queued Packet Switches,” Proc. IEEE Sarnoff Symposium 2006, 27-28 March 2006.

 

 

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Matching Schemes with Frame Occupancy-based Eligibility for Input-Queued Packet Switches” Proceedings of IEEE International Conference on Communications 2005, vol. 2, pp. 972-976, Seoul, Korea, May 16-20 2005.

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Frame Occupancy-based Round-Robin Matching (FORM) for Input-Queued Packet Switches,” Proceedings of IEEE Globecom 2004, vol. 3, pp. 1845-1849, November 2004.

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Captured-Frame Eligibility and Round-Robin Matching for Input-queue Packet Switches,” IEEE Communication Letters, vol.8, issue 9, pp. 585-587, September 2004.

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Roberto Rojas-Cessa, Robert Nawrocki, Darine Abisaleh, Ankita Raut, Pratik Sheth, Suhasini Madidi, Justus Srigiri, Shukri Abdelhalim, and Mohammed Abumokhemar, “Implementation of Scheduling Algorithms for Input-Queued Packet Switches: an Undergraduate Senior Project Experience,” Proceedings of the X Workshop Iberchip, Cartagena, Colombia, March 2004.

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Simulation of Maximal Scheduling Schemes for Input-Queued Packet Switches,” Proceedings of Conference on Information Systems and Sciences, Princeton University, Princeton, NJ, April 2003.

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Eiji Oki, Roberto Rojas-Cessa, and H. Jonathan Chao, “A Pipelined Maximal-size Matching Scheme for Input-buffered Switches,” IEICE Transactions on Communications, Vol.E85-B, No.7, pp. 1302-1311, July 2002.

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Eiji Oki, Roberto Rojas-Cessa, and H. Jonathan Chao, “Pipelined-based Approach for Maximal-size Matching Scheduling in Input-buffered Switches,” IEEE Communication Letters, Vol. 5, Issue 6, 363-365, June 2001.

 

 

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 Eiji Oki, Roberto Rojas-Cessa, and H. Jonathan Chao, “PMM: Pipelined Maximal-size Matching Scheduling Approach for Input-buffered Switches,” Proceedings of IEEE Globecom 2001, Vol. 1, pp. 35-39, Dallas, TX, November 2001.

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Buffered Crossbar Switches

 

 

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Ziqian Dong and Roberto Rojas-Cessa, “Input- and Output-Based Shared-Memory Crosspoint-Buffered Packet Switches for Replicating and Switching Multicast Traffic,” accepted in IEEE International Conference of Communications 2008, Beijing, China, May 2008.

 

 

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Ziqian Dong and Roberto Rojas-Cessa, “Output-based Shared-Memory Crosspoint-Buffered Packet Switch for Multicast Services,” IEEE Commun. Letters, December 2007.

 

 

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Ziqian Dong and Roberto Rojas-Cessa, “Efficient Packet Replication and Switching of Multicast Traffic by Shared-Crosspoint Buffer Switch,” Proc. IASTED International Conference on Communication Systems, Networks and Applications (CSNA 2007), Beijing, China, October 2007.

 

 

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Ziqian Dong and Roberto Rojas-Cessa, “Packet Switching and Replication of Multicast Traffic by Crosspoint Buffered Packet Switches,” accepted in IEEE HPSR, May 2007.

 

 

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Zhen Guo and Roberto Rojas-Cessa, “Explicit Feedback Arbitration Scheme for Crosspoint Buffered Packet Switches,” accepted in IEEE HPSR, May 2007.

 

 

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Ziqian Dong and Roberto Rojas-Cessa, “Shared-Memory Combined Input-Crosspoint Buffered Packet switch for Differentiated Services,” accepted in IEEE Globecom, November 2006.

 

 

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Roberto Rojas-Cessa, Zhen Guo, and Nirwan Ansari, “On the Maximum Throughput of a Combined Input-Crosspoint Buffered Packet Switch,” IEICE Transactions on Communications, vol. E89-B, no. 11, pp. 3120-3123, November 2006.

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Zhen Guo and Roberto Rojas-Cessa, “Framed Round-Robin Arbitration with Explicit Feedback Control for Combined Input-Crosspoint Buffered Packet Switches,” accepted in IEEE International Conference on Communications 2006, Istanbul, Turkey, 11-15 June 2006.

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Roberto Rojas-Cessa and Ziqian Dong, “Combined Input-Crosspoint Buffered Packet Switch with Flexible Access to Crosspoint Buffers,” accepted in IEEE International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen, Mexico, April 2006.

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Roberto Rojas-Cessa and Zhen Guo, “Round-Robin with Adaptable-Size Frame Arbitration for Combined Input-Crosspoint Buffered Packet Switch,” IEICE Transactions on Communications, vol. E89-B, no. 5, pp. 1495-1504, May 2006.

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Roberto Rojas-Cessa, Ziqian Dong, and Sotirios G. Ziavras, “Load-Balanced Combined Input-Crosspoint Buffered Packet Switch with Long Round-Trip Time Support,” Proceedings of IEEE Globecom 2005, vol.2, pp. 1002-1006, Saint Louis, MO, November 2005.

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Roberto Rojas-Cessa, Zhen Guo, and Nirwan Ansari, “Combining Distributed and Centralized Arbitrations in Combined Input-Crosspoint Buffered Packet Switches,” accepted in IEEE International Conference on Networks, Kuala Lumpur, Malaysia, November 2005.

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Roberto Rojas-Cessa, Eiji Oki, and H. Jonathan Chao, “On the Combined Input-Crosspoint Buffered Packet Switch with Round-Robin Arbitration,” IEEE Transactions on Communications, Vol. 53, No. 11, pp. 1945-1951, November 2005.

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Ziqian Dong and Roberto Rojas-Cessa, “Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch,” Proceedings of IEEE 13th Annual Symposium on High Performance Interconnects, pp. 138-143, 17-19, Palo Alto, CA, August 2005.

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Roberto Rojas-Cessa, Ziqian Dong, and Zhen Guo, “Load-Balanced Combined Input-Crosspoint Buffered Packet Switch and Long Round-Trip Times,” IEEE Communications Letters, vol. 4, issue 7, pp. 661-663, July 2005.

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Zhen Guo and Roberto Rojas-Cessa, “Analysis of a Flow Control for Combined Input-Crosspoint Buffered Packet Switch,” Proceedings of the IEEE Workshop on High Performance Switches and Routers, pp. 336-340, Hong Kong, China, May 2005.

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Roberto Rojas-Cessa and Ziqian Dong, “Combined Input-Crosspoint Buffered Packet Switch with Shared Crosspoint Buffers,” Proceedings of the 39th Conference on Information Sciences and Systems, John Hopkins University, Baltimore, MD, March 16-18, 2005.

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Zhen Guo and Roberto Rojas-Cessa, “Stability Analysis of a Flow Control for Combined Input-Crosspoint Buffered Packet Switch,” Proceedings of the 39th Conference on Information Sciences and Systems, John Hopkins University, Baltimore, MD, March 16-18, 2005.

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Roberto Rojas-Cessa, "Adaptable-size Frame with Round-robin Arbitration for Input-Crosspoint Buffered Switches," Proceedings of IEEE International Conference on Communications, pp. 1113-1117, vol. 2, Paris, France, June 20-24, 2004.

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Roberto Rojas-Cessa, “High-Performance Arbitration Schemes for Input-Crosspoint Buffered Switches," Proceedings of IEEE Workshop on High Performance Switches and Routers 2004, pp. 167-171, Phoenix, AZ, April 2004.

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Roberto Rojas-Cessa and Eiji Oki, “Round-robin Selection with Adaptable-size Frame in a Combined Input-Crosspoint Buffered Switch,” IEEE Communications Letters, vol. 7, issue 11, pp. 555-557, November 2003.

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Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao, “CIXOB-k: Combined Input-Crosspoint-Output Buffered Switch,” Proceedings of IEEE Globecom 2001, Vol. 4, pp. 2654-2660, Dallas, TX, November 2001.

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Roberto Rojas-Cessa, Eiji Oki, Zhigang Jing, and H. Jonathan Chao, “CIXB-1: Combined Input-One-Cell-Crosspoint Buffered Switch,” Proceedings of IEEE Workshop of High Performance Switches and Routers 2001, pp. 324-329, Dallas, TX, May 2001.

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Clos-Network Switches

 

 

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Chuan-Bi Lin and Roberto Rojas-Cessa, “Module Matching Schemes for Input-Queued Clos-Network Packet Switches, “ accepted in IEEE ICC 2008, Beijing, China, 2008.

 

 

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Chuan-Bi Lin and Roberto Rojas-Cessa, “Module Matching Schemes for Input-Queued Clos-Network Switches,”  IEEE Communications Letters, vol. 11, No.2, pp. 3 pages, February 2007.

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Roberto Rojas-Cessa and Chuan-Bi Lin, “Scalable Two-Stage Clos-Network Packet Switch and Module Matching,” IEEE Workshop on High Performance Switching and Routing, May 2006.

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Chuan-Bi Lin and Roberto Rojas-Cessa, “Framed Occupancy-Based Dispatching Schemes for Buffered Clos-Network Packet Switches,” Proceedings of IEEE International Conference on Networks 2005, 5p, Kuala Lumpur, Malaysia, November 2005.

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Roberto Rojas-Cessa, Eiji Oki, and H. Jonathan Chao, “Maximum Weight Matching Dispatching for Buffered Clos-networks,” Proceedings of the IEEE International Conference in Communications, vol. 2, pp. 1075-1079, Paris, France, June 2004.

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Eiji Oki, Zhigang Jing, Roberto Rojas-Cessa, and H. Jonathan Chao, “Concurrent  Round-Robin-Based Dispatching Schemes for Clos-Network Switches,” IEEE/ACM Transactions on Networking, vol. 10, issue 6, pp. 830-844, December 2002.

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Eiji Oki, Roberto Rojas-Cessa, and H. Jonathan Chao, “PCRRD: A Pipelined-based Concurrent Round-Robin Dispatching Scheme for Clos-Network Switches,” Proceedings of IEEE International Conference on Communications 2002, vol. 4, pp. 2121-2125, New York, NY, April 2002.

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Eiji Oki, Zhigang Jing, Roberto Rojas-Cessa, and H. Jonathan Chao, “Concurrent Round-Robin Dispatching Scheme for a Clos-network Packet Switch,” Proceedings of IEEE International Conference on Communications 2001, Vol. 1, pp. 107-111, Helsinki, Finland, June 2001.

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Fault Tolerance and Reliability

 

 

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Roberto Rojas-Cessa, Eiji Oki, and H. Jonathan Chao, “Concurrent Schemes for Fault Detection in a Multiple-plane Switch,” IEEE/ACM Transactions on Networking, Vol. 11, Issue 4, pp. 616-627, August 2003.

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Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao, “Fast fault Detection Schemes for a Multiple-Plane Packet Switch,” Proceedings of IEEE Globecom 2001, Vol. 1, pp. 102-109, Dallas, TX, November 2001.

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Network Security and QoS

 

 

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Kanchan Devarakonda, Sotirios G. Ziavras, and Roberto Rojas-Cessa, “Measuring Network Parameters with Hardware Support,” in Proceedings of IEEE International Conference on Networking and Services,” 6 pages, Athens, Greece, June 2007.

 

 

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Zhen Qin, Roberto Rojas-Cessa and Nirwan Ansari, “Descending-Order Clique-Based Task Scheduling for Active Measurements,” accepted in IEEE HPSR, May 2007.

 

 

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Zhen Qin, Roberto Rojas-Cessa and Nirwan Ansari, “Distributed Link-State Measurement for QoS Routing,” accepted in IEEE MILCOM 2006, Washington, DC, October 23-25, 2006.

 

 

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Zhen Qin, Roberto Rojas-Cessa, and Nirwan Ansari, “OSPF-Based Adapted and Flexible Security-Enhanced QoS Provisioning,” accepted in IEEE Sarnoff Symposium 2006, Princeton NJ, 26-28 March 2006.

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Pitipatana Sakarindr, Nirwan Ansari, and Roberto Rojas-Cessa, “Information Assurance in the QoS Network,” accepted in IEEE Sarnoff Symposium 2006, Princeton NJ, 26-28 March 2006.

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Pitipatana Sakarindr, Nirwan Ansari, Roberto Rojas-Cessa, and Symeon Papavassiliou “Security-enhanced Quality of Service (SQoS): A Network Analysis,” Proceedings of 2005 IEEE MILCOM, pp. 1-7, October 2005.

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Pitipatana Sakarindr, Nirwan Ansari, Roberto Rojas-Cessa, and Symeon Papavassiliou “Security-enhanced Quality of Service (SQoS): Design and Architecture,” Proceedings of 2005 IEEE Sarnoff Symposium, pp. 129-132, April 2005.

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Miscellaneous

 

 

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Roberto Rojas-Cessa, Lakshmi Ramesh, Ziqian Dong, and Nirwan Ansari, “Parallel-Search Trie-Based Scheme for Fast IP Lookup,” Proc. IEEE Global Telecommunications Conference, Globecom 2007, Washington, DC, November 2007.

 

 

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Roberto Rojas-Cessa, Lakshmi Ramesh, Ziqian Dong, Brian D’Alessandro, and Nirwan Ansari, “Implementation of a Parallel-Search Trie-Based Scheme for Fast IP Lookup,” accepted in IASTED International Conference on Communication Systems, Networks, and Applications, CSNA 2007, Beijing, China, October 2007.

 

 

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N. Ansari, C. Zhang, R. Rojas-Cessa, S. De, P. Sakarindr, and E.S.H. Hou, “Network for Critical Conditions,” accepted in IEEE Wireless Communications, 2007.

 

 

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Roberto Rojas-Cessa, “Design of a 5-priority 128K-cell Input Queue Controller for an ATM Switch,” Proceedings of IV Iberchip Workshop, Lima, Peru 1999.

 

 

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Roberto Rojas-Cessa and Gustavo Urena, “Implementation of a Routing Address Generation and Cell Address Translation Chip with VHDL,” Workshop of Mentor Graphics Applications, Connecticut, 1997.

 

 

Biomedical

 

 

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Roberto Rojas Cessa, Joaquin Remolina Lopez, “Muscle-Contraction Linear displacement Evaluation System for Clinical use,” Proceedings of II Iberchip Workshop, vol. II, Sao Paolo, Brazil, 1996.

 

 

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Roberto Rojas Cessa and Joaquin Remolina Lopez, “Design and implementation of a Digital Clinical Neuron-stimulator in an Integrated Circuit,” Proceedings of I Iberchip Workshop, Colombia 1995.

 

 

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Joaquin Remolina Lopez and Roberto Rojas Cessa, “Neuron-stimulator Integrated Circuit for Clinical evaluation of Neuromuscular Pharmacologically Induced Blockade,” Proceedings of the 1st. Conference on Electrical Engineering at CINVESTAV, Mexico, 1995.

 

 

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Joaquin Remolina Lopez and Roberto Rojas Cessa, “Electrical Stimulator of Clinical Use for the Degree Detection of Pharmacological Neuromuscular Blockade: a Digital Solution,” Mexican Magazine of Biomedical Engineering, vol. 15, 1994.

 

 

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Joaquin Remolina Lopez, Roberto Rojas Cessa, “Electrical Stimulator for the detection of Pharmacological Neuromuscular Degree of Blockade: an Analogical Solution for Clinical Use,” Mexican Magazine of Biomedical Engineering, vol. 14, 2, 1993.  

 

Invited Talks

 

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Research Trends in Next Generation Networks: Switching and Routing, Thammasat University, Rangsit Campus, Pathumthani, May 2005, Thailand.

 

 

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Conmutadores de Alta Capacidad y Alto Rendimiento, Instituto Tecnolσgico Superior de Acayucan (ITSA), November 2004, Mexico.

 

 

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Overview of Network Processors, Chinese Institute of Engineers/ Greater New York Chapter (CIE-USA/GNYC), 2002 Annual Convention, Oct. 2002, Newark NJ.

 

 

Book Chapter

 

 

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Zhen Guo, Roberto Rojas-Cessa, and Nirwan Ansari, “Chapter: Packet Switches with Internally Buffered Crossbars,” in “High Performance Switch Architectures,” ISBN: 1-84628-273-X, Springer, September 2006.

 

 

 

Patents

 

 

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U.S. patent No. 7,046,661, “Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme,” Co-inventor, May 16, 2006.

 

 

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U.S. patent No. 7,006,512, “Pipelined maximal-sized matching cell dispatch scheduling,” Co-inventor, February 28, 2006.

 

 

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U.S. patent No. 6,940,851, “Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme,” Co-inventor, September 6, 2005.