Shuai Wang Ph.D. Candidate Electrical and Computer Engineering New Jersey Institute of Technology

211B Faculty Memorial Hall New Jersey Institute of Technology University Heights Newark, NJ 07102 Email: sw63 at njit dot edu Web: http://web.njit.edu/~sw63

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Recent News:

CFP: 21st International Conference on Tools with Artificial Intelligence (ICTAI 2009)

Course: ECE 252 Microprocessors, Summer 2009

Biography:

I am now a Ph.D. candidate (expected to graduate in December 2009) in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, advised by Prof. Jie Hu. I received my B.S. degree in computer science from Nanjing University.

I am currently a member of CAPPL (Computer Architecture and Parallel Processing Laboratory) Research Group.

• Curriculum Vitae

Research Interests:

My research interests are broadly in computer architecture and systems, with current focuses mainly on power/thermal-aware systems design, reliable microarchitecture and systems design, embedded systems, high performance computing, and on-chip networks.

Publications:

Journals:

• Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Transactions on Computers (TC), Volume 58, Issue 9, pp. 1171 - 1184, September 2009. (PDF)
• Jie Hu, Shuai Wang, and Sotirios G. Ziavras. On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 17, Issue 7, pp. 953 - 963. July 2009. (PDF)
• Jie Hu, Johnsy K. John, and Shuai Wang. Thermal-Aware Subarrayed Data Cache Microarchitectures. International Journal of Intelligent Control and Systems (IJICS), Volume 13, No. 4, pp. 251 - 263, December 2008. (PDF)
• Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 27, Issue 8, pp. 1503 - 1507, August 2008. (PDF)
• Shuai Wang, Hongyan Yang, Jie Hu, and Sotirios G. Ziavras. Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance. Microprocessors and Microsystems, Volume 32, Issue 3, pp. 171 - 182, May 2008. (PDF)

Conferences:

• Shuai Wang, Jie Hu, Sotirios G. Ziavras, and Sung Woo Chung. Exploiting Narrow-Width Values for Thermal-Aware Register File Designs. In Proc. of the Conference on Design, Automation and Test in Europe (DATE 2009), pp. 1422 - 1427, Nice, France, April 20-24, 2009. (accepted 226 out of 965 submissions, acceptance rate: 23%) (PDF)
• Shuai Wang, Jie Hu, and Sotirios G. Ziavras. BTB Access Filtering: A Low Energy and High Performance Design. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81 - 86, Montpellier, France, April 7-9, 2008. (accepted 74 out of 245 submissions, acceptance rate: 30%) (Best Paper Award Nomination) (PDF)
• Shuai Wang, Hongyan Yang, Jie Hu, and Sotirios G. Ziavras. Asymmetrically Banked Value-Aware Register Files. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 363 - 368, Porto Alegre, Brazil, May 9-11, 2007. (accepted 66 out of 174 submissions, acceptance rate: 38%) (PDF)
• Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, and Jie Hu. Vector Processing Support for FPGA-Oriented High Performance Applications. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 447 - 448, Porto Alegre, Brazil, May 9-11, 2007. (Poster, accepted 27 out of 174 submissions) (PDF)
• Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. In Proc. of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS VI),  pp. 14 - 20, Samos, Greece, July 17-20, 2006. (accepted 26 (for IC-SAMOS) out of 130 submissions, acceptance rate: 20%) (PDF)
• Jie Hu, Shuai Wang and Sotirios G. Ziavras. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN 2006) - Dependable Computing and Communications Symposium (DCCS), pp. 281 - 290, Philadelphia, PA, June 25-28, 2006. (accepted 34 out of 187 submissions, acceptance rate: 18%) (PDF)
• Jie Hu, Greg M. Link, Johnsy John, Shuai Wang, Sotirios G. Ziavras. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. In Proc. of the Asia-Pacific Computer Systems Architecture Conference (ACSAC 2005), pp. 200 - 214, Singapore, October 24-26, 2005. (accepted 65 out of 173 submissions, acceptance rate: 37%) (PDF)

Talks:

• BTB Access Filtering: A Low Energy and High Performance Design, at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), Montpellier, France, April 7-9, 2008.
• Asymmetrically Banked Value-Aware Register Files, at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), Porto Alegre, Brazil, May 9-11, 2007.

Teaching:

• ECE 252: Microprocessors
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• ECE 495: Computer Engineer Design Lab         
  This lab emphasizes hardware design and debugging. Topics include combinational and sequential logic design using CAD tools, VHDL, and design based upon PLA/PLD.

Member: ACM, ACM SIGARCH, IEEE, IEEE Computer Society

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