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Computer Science Course Information

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Computer Architecture

Course No. CIS 650
Sections 101
Title Computer Architecture
Course Website
Prerequisite(s) Undergraduate digital logic course such as CS251,
Undergraduate computer organization course such as CS353, general knowledge in
assembly language and C programming language.
Instructor Andrew Sohn
  • Office Room No. : GITC 4209
  • Office Phone : 973-596-2315
  • Fax : 973-596-5777
  • Email :
  • Website:
  • Lab : N/A
  • Instructor Office Hours
    Description Study of modern computer organizations, including integer and
    floating arithmetic, pipelining, instruction level parallelism and its
    exploitation, cache memory, main memory, disk, bus structure, introduction of
    multiprocessors, and clustering of multiple machines.
    Topics Introduction, bus architecture (self reading)
    Integer arithmetic,floating point arithmetic
    Basic pipelining concepts
    Pipelining hazards
    Instruction level parallelism
    Exploiting instruction level parallelism
    Cache memory,Main memory, virtual memory
    Storage systems, NAS, SAN, iSCSI, blade-based
    Interconnection networks
    Clustering and beyond.
    Text Book(s) Text Book: Computer Architecture, Hennessy and Patterson, 3rd Ed. ISBN: 1-55860-596-7, Publisher: Elsevier
    - Computer Organization and Design, Patterson and Hennessy, 3rd Ed., Elsevier
    - Computer Arithmetic Algorithms, I. Koren, Prentice Hall
    Time & Place Monday 6:00 PM - 9:05 PM, Kupf 117
    Other Info Grading: homework (0%), Test 1 (20%), Test 2 (20%), Test 3 (20%), Final exam (30%), Project (10%)Grading: homework (0%), Test 1 (20%), Test 2 (20%), Test 3 (20%), Final exam (30%), Project (10%)
    Homework has no weight. However, you are strongly encouraged to try the homework given in the previous semesters to further your udnerstanding
    Exams are closed books, closed notes. No make-up exams. Tests 1-3 will be held in the first half of class 6pm-7:30pm (1 hour 30 mins). There will be a lecture in the second half (8-9 pm) after 30 min break.
    Project: Due 11:59 pm, Wednesday, 12/7/2005. Check the web page for details. Project descripton will be posted by the end of September or early October.

    Class Schedule by Week

    H&P Chs 1-2, introduction, bus architecture (self reading)
    H&P Appendix H, P&H Ch4 integer arithmetic
    H&P Appendix H, P&H Ch4 integer arithmetic
    H&P Appendix H, P&H Ch4 floating point arithmetic
    Test 1, 6:00-7:30 PM, Monday, 10/3/2005
    Lecture 8-9 pm: H&P Appendix A, P&H Chs5-6 basic pipelining concepts
    H&P Appendix A, P&H Chs5-6 pipelining hazards
    H&P Ch 3 instruction level parallelism
    H&P Chs 3-4 instruction level parallelism and exploiting instruction level parallelism
    Test 2, 6:00-7:30 PM, Monday, 10/31/2005
    Lecture 8-9 pm: H&P Ch 4 exploiting instruction level parallelism
    H&P Ch 5 cache memory
    H&P Ch 5 main memory, virtual memory
    H&P Ch 7 storage systems, NAS, SAN, iSCSI, blade-based
    Test 3, 6:00-7:30 PM, Monday, 11/28/2005
    Lecture 8-9 pm: H&P Ch 8 interconnection networks
    H&P Ch 8 interconnection networks
    H&P Ch 6 multiprocessors
    Virtualization, virtual machines, clustering, and beyond
    Final Exam, 6:00-8:30 PM, Monday, 12/19/2005
    P&H = Patterson & Hennessy, Computer Organization and Design, 3rd ed., Elsevier
    H&P = Hennessy & Patterson, Computer Architecture, 3rd ed., Elsevier

    Academic Honor Code

    The NJIT academic honor code
    ( in full to this
    class. Note in particular that copying programs, in full or in part, is
    forbidden. You may discuss ideas and concepts with your fellow
    students, but you may NOT copy any code.

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