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Level >Graduate >FALL_2005 >List >

Computer Architecture

Course No. CIS 650
Sections 103, 105
Title Computer Architecture
Course Website
Prerequisite(s) Logic Design
Basics of Computer Organization
Assembly Language Programming
C/C++ or JAVA Programming
Instructor Alexander Thomasian
  • Office Room No. : GITC 4314
  • Office Phone : 973-596-6597
  • Fax : 973-596-5777
  • Email :
  • Website:
  • Lab : N/A
  • Instructor Office Hours
    Description Exploiting instruction level parallelism (ILP) is central to designing modern computers. Presents design techniques used for such computers as IBM Power architectures, DEC Alpha, MIPS R4600, Intel P6, etc. Introduction of Instruction Set Architecture (ISA), various functional units, basic principles of pipelined computers. Modern techniques to ILP including superscalar, super-pipelining, software pipelining, loop unrolling, and VLIW. Memory hierarchy, including instruction cache, data cache, second level cache, and memory interleaving. Advanced computer architectures, including vector, array processors, interconnection technology, and ATM network of workstations. Hands-on experience designing a simple pipelined computer on screen and using CAD tools such as Cadence or ViewLogic.
    Topics MIPS Programming
    Computer Arithmetic
    Processor Datapath and Control
    Instruction Level Parallelism
    ILP via Software
    Cache and Virtual Memory
    I/O Systems and Perfomance Analysis
    Multicomputers and Computer Clusters
    Text Book(s) Computer Architecture: A Quantitative Approach,3rd edition by Hennessy and Patterson.
    Morgan Kaufmann Publishers Inc.
    Time & Place Section 103 Thursdays KUPF 118
    Section 105 Tuesday Culm Lec # 1
    Other Info Academic Honor Code

    The NJIT academic honor code
    ( in full to this
    class. Note in particular that copying programs, in full or in part, is
    forbidden. You may discuss ideas and concepts with your fellow
    students, but you may NOT copy any code.

    Registrar's Website