VHDL

VHDL is Very High Speed Integrated Circuit (VHSIC) hardware description language (HDL). We are going to use this HDL for rest of tutorial. Some tips to write successful code are given below:

1) Some VHDL codes are only for the simulation purpose, for example Test Benches. Most of the constructs used in Test Benches are like C.  High level constructs like for while loops can be used much easier to write a good Test Bench. The important thing to understand in VHDL is that all the constructs are not synthesizable i.e. synthesizer is not able to provide hardware for each and every construct in VHDL. Take following assignment:

                y<= a and b after 5 ns

In this signal assignment after evaluating the right hand side expression, value to y is assigned after 5 ns. This code can be simulated but it is not synthesizable. When writing a code for hardware generation do not use the constructs which are not synthesizable.

2) Always partition your project into modules. Divide the functionality between modules in such a way that the internal details of one module doesn't interfere with other modules. Define interface for all the modules so that each and every programmer can understand what inputs he/she is getting and what outputs he/she have to provide. Simulate and synthesize each and every module to verify the functionality and other desired parameters. After completion of all the modules instantiate them in one top file by using structural modeling. Use proper signals and expression to interface all the modules properly and simulate and synthesis again to check the consistency.