Ph.D., Distinguished Professor    
Department of Electrical and Computer Engineering    
New Jersey Institute of Technology    
University Heights  
Newark, New Jersey 07102-1982  
Phone: (973) 596-5681    
Email: savir@oak.njit.edu    

• Test Generation: this field of research deals with efficient computation of test vectors to detect manufacturing faults in digital circuits.

• Fault Simulation: this field of investigation deals with efficient simulation techniques to determine which faults are detected by a given test. 

• Design for Testability: this field of research deals with innovative ways to make a design more testable, i.e reducing the test generation time, and increasing the fault coverage. 

• Computer-Aided Design: this field of research deals with automatic design tools for digital circuits. 

• Built-In Self-Test (BIST): this field of research deals with innovative structured design methodology that will allow a digital circuit to test itself. 

•  J. Savir, ''Random Pattern Testability of the Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections,'' Journal of Electronic Testing, vol. 15, No. 3, pp. 279-296, Dec. 1999.

•  J. Savir, ''Distributed Generation of Weighted Random Patterns,'' IEEE Trans. Comput., vol. 48, No. 12, pp. 1364-1368, Dec. 1999.

•  J. Savir, ''On-Chip Weighted Random Patterns,'' Journal of Electronic Testing, vol. 13, No. 1, pp. 41-50, Aug. 1998.

•  J. Savir, ''Random Pattern Testability of Memory Address Logic,'' IEEE Trans. on CAD, vol. 17, pp. 1310-1318, Dec. 1998.

•  J. Savir, ''Redundancy Revisited,'' IEEE Trans. on VLSI, vol. 6, No. 4, pp. 620-624, Dec. 1998.

•  J. Savir, ''On-Chip Weighted Random Patterns,'' Journal of Electronic Testing, vol. 13, No. 1, pp. 41-50, Aug. 1998.

•  J. Savir, ''Salvaging Test Windows in BIST Diagnostics,'' IEEE Trans. Comput., vol. 47, No. 4, pp. 486-491, April 1998.

•  J. Savir, ''Random Pattern Testability of Memory Control Logic,'' IEEE Trans. Comput., vol. 47, No. 3, pp. 305-312, March 1998.

•  J. Savir, ''Reduced Latch Count Shift Registers,'' Journal of Electronic Testing, vol. 11, No. 2, pp. 183-185, Oct. 1997.

•  J. Savir, ''Delay Test Generation: A Hardware Perspective,'' Journal of Electronic Testing, vol. 10, No. 3, pp. 245-254, June 1997.

•  J. Savir, ''Module Level Weighted Random Patterns,'' Journal of Electronic Testing, vol. 10, No. 3, pp. 283-287, June 1997. 

•  J. Savir, ''Reducing the MISR Size,'' IEEE Trans. Comput., vol. 45, No. 8, pp. 930-939, August 1996. 

•  J. Savir ''Shrinking Wide Compressors,'' IEEE Trans. on CAD, vol. 14, No. 11, pp. 1379-1387, Nov. 1995. 

•  J. Savir and S. Patil, ''On Broad-Side Delay Test,'' IEEE Trans. on VLSI, vol. 2, No. 3, pp. 368-372, Sept. 1994. 

•  J. Savir and S. Patil, ''Broad-Side Delay Test,'' IEEE Trans. on CAD, vol. 13, No. 8, pp.1057-1064, Aug. 1994. 

•  J. Savir and P.H. Bardell, ''Built-in Self-Test: Milestones and Challenges,'' Gordon and Breach Science Publishers, VLSI   Design, vol. 1, No. 1, pp. 23-44, 1993. 

•  J. Savir and S. Patil, ''Scan-Based Transition Test,'' IEEE Trans. on CAD, vol. 12, No. 8, pp. 1232-1241, August 1993. 

•  J. Savir and R. Berry, ''AC Strength of a Pattern Generator,'' J. on Electronic Testing, Issue 2, vol. 3, pp. 119-125, May 1992.

•  J. Savir and W.H. McAnney, ''A Multiple Seed Linear Feedback Shift Register,'' IEEE Trans. Comput., vol. 41, No. 2, pp. 250-252, Feb. 1992. 

• Bardell, McAnney & Savir: "Built-In Testing for VLSI: Pseudorandom Techniques"; Wiley Interscience; 1987 

• Ph.D. Electrical Engineering, 1978, Stanford University     

• MS Statistics, 1976, Stanford University     

• M.Sc. Electrical Engineering, 1974, Technion, Israel Institute of Technology

• B.Sc. Electrical Engineering, 1968, Technion, Israel Institute of Technology

Experience 

  A. Academic Appointments 

• Newark College of Engineering Associate Dean for Research,  New Jersey Institute of Technology, 1999-2000 

• Distinguished Professor & Director of Computer Engineering,  New Jersey Institute of Technology, 1996-2000 

                                       

• Adjunct Professor, Pace University, 1979-93 

• Adjunct Professor, SUNY Purchase, 1989 

• Adjunct Lecturer, Technion, Israel Institute of Technology, 1972-75 

• Adjunct Lecturer, Technion-Handasaiim, Israel Institute of Technology,  1972-75

• Adjunct Lecturer, Ort Syngalovsky, 1968-75 

• Adjunct Lecturer, Technion, Israel Institute of Technology , 1967 

  B. Non-Academic Employment   

• Scientist, IBM, PowerPC, 1995-96     

• Scientist, IBM, Hudson Valley Research Park, 1993-95 

• Scientist, IBM, Enterprise Systems, 1982-93     

• Research Staff Member, IBM, T.J. Watson Research Center, 1978-82 

 

Patents Awarded   

• J. Savir:  Scan-based delay tests having enhanced test vector pattern generation;  US 5,642,362; filed: 6/18/92, issued: 6/24/97. 

• P.H. Bardell and J. Savir: Test and diagnosis of associated output logic for products having embedded arrays,  US 5,442,640; filed:1/19/93; issued: 8/15/95. 

• J. Savir: Universal weight generator, US 5,394,405; filed: 1/17/91; issued: 2/28/95. 

• R. Berry and J. Savir: Delay test coverage enhancement for logic circuitry employing level sensitive scan design, US 5,278,842; filed: 2/4/91; issued: 1/11/94. 

 

Professional Societies   

• Fellow,  IEEE.     

• Member,  Sigma-Xi.     

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