Course Syllabus

Class Web page: http://www.cs.njit.edu/~sohna/cs650

Note the three exam dates. There will be no makeup exams. Plan your semester accordingly. No show for the final exam will result in failure in the exam, and in turn in the course unless it's emergency. You will be asked for proof of such emergency if applicable.

Check the FAQs and announcements pages regularly. Read them before you call or send me email. You will not get my response to the questions to which the answers have already been posted.

Instructor: Andrew Sohn, GITC4209, (973)596-2315, email: sohn at cs dot njit dot edu
Office Hours:TBA
Teaching Assistant: TBA
Class time and location: 6-9 pm, Thur
Text Book: Computer Architecture, Hennessy and Patterson, 5th Ed. ISBN: 9780123838728, Publisher: Elsevier
References:
- Computer Organization and Design, Patterson and Hennessy, 4th Ed., Elsevier
- Computer Arithmetic Algorithms, I. Koren, Prentice Hall
Grading: Homework (x%), Project (y%), Test 1 (z%), Test 2 (w%), Final exam (p%)
Project: TBA
Exams are closed books, closed notes. No make-up exams.
The NJIT Honor Code: You are required to read and follow the NJIT Honor Code.

Class Schedule by Week (tentative - will be finalized before semester begins)

  1. Classes of computers (Ch.1), PC Organization (Web): motherboard (ATX), microprocessor, bus architecture, chipset, POST, BIOS, and MBR.
    Integer Arithmetic (Appendix J): fast adders.
  2. Integer Arithmetic: fast multipliers. Floating Point Arithmetic (Appendix J): adder, multiplier, SRT divider, QCD divider.
  3. Basic Pipelining (Appendix C): pipelining concepts, hazards detection and resolution, forwarding and bypassing, delayed branch, exception handling.
  4. Instruction Level Parallelism (Ch.3): compiler techniques, dynamic instruction scheduling, register renaming, branch prediction.
  5. Test 1, 6-7:15 pm. Lecture 7:30-9 pm: Instruction Level Parallelism (Ch.3): speculation, hardware multithreading, Compiler-based scheduling, loop unrolling, software pipelining.
  6. Memory hiearchy (Appendix B and Ch.2): logical, linear/virtual, physical memory. Cache Memory: L1, L2, and L3 cache organization, mapping, placement, replacement, identification, write policies, cache hit/miss rate and penalty
  7. Memory hiearchy (Appendix B and Ch.2): Main memory: cell organization, row and column accesses, SDRAM, DDR3, DIMM card, memory interleaving, address translation in segmentation and paging.
  8. Data-level parallelism (Ch.4): Vector architecture, SIMD instruction set extension, GPU architectures, detecting and enhancing loop-level parallelism
  9. Thread-level parallelism (Ch.5 - Optional): Centralized shared-memory machines, synchronization mechanisms, memory coherence protocols.
  10. Test 2, 6-7:15 pm. Lecture 7:30-9 pm: Datacenter-scale computers (Ch.6): physical infrastructre, distributed-memory machines, cluster of PCs and their programming models
  11. Storage and file system (Appendix D & Web): disk, RAIDs, DAS, NAS, SAN, iSCSI, blade storage, their protocols, comparisons.
  12. Networking and interconnection networks (Appendix F & Web): NIC, IRQs, DMA, networking media, switching technology, basic routing algorithms, network topology, switch architecture
  13. Programming many cores, many physical/virtual machines and cluster of physical/virtual machines: Message Passing Interface (MPI) for many-core distriburted-memory machines (possibly Open MP for shared-memory machines)
  14. Datacenter infrastructure, virtualization, virtual machine monitors (KVM and Xen), managing virutual machines, virtual machine migration, load balancing datacenter machines.
  15. Final exam, 6-8:30 PM, Thur, 12/20/2012