NJITElectrical and Computer Engineering Department


Computer Architecture 


Parallel Processing Laboratory (CAPPL)


Link to CAPPL Research Facilities


Among many recent CAPPL Laboratory innovations, Dr. Ziavras’s CAPPL research group pioneered:

·                     The concept of end-user programmable semi-customized multicores for high-performance embedded computing using FPGAs (in 2002). Floating-point units were included in the multicores.

·                     The concept of vector coprocessor sharing for multicores embedded in FPGAs (in 2005).

·                     The concept of vector coprocessor sharing in general-purpose multicores. Various runtime policies were introduced in order to maximize the performance while also minimizing the overall energy consumption (static and dynamic energy); this work was benchmarked using FPGA-based prototypes as well as ASIC (Application-Specific Integrated Circuit) implementations (in 2010).

·                     The first known implementation of LU (Lower-Upper triangular) factorization on FPGAs using multicores with floating-point units (in 2003). LU factorization is of paramount importance to scientific and high-performance computing. Our approach for huge sparse matrices has since been also used by the EDA (Electronic Design Automation) industry to speedup circuit simulation.

·                     A new scalability definition for parallel computing based on a directional derivative of performance in a multidimensional space (in 2005). Expanding all the design dimensions of interest and collapsing all the other dimensions, this kind of scalability evaluation facilitates an analysis to find an optimal path to scale up a system for a given problem solution; it also supports a comparison of potential solutions.

·                     Parallel solution of Newton’s power-flow equations on multiprocessors embedded in FPGAs in an effort to facilitate real-time monitoring of the Power Grid (in 2006).

·                     FPGA-based network intrusion detection involving real-time pattern matching that also facilitates (the concept of) efficient runtime pattern updates (in 2009).

·                     The concept of dynamic/runtime resource and energy management for reconfigurable mixed-mode multiprocessors (i.e., simultaneously supporting the SIMD and MIMD parallel execution modes) embedded in FPGAs (in 2005).

·                     Online privacy protection in computer-mediated communication using information-entropy based realistic estimation of user anonymity levels, along with high-performance implementations (joint work, in 2009).

·                     The concept of ASIC design for very high performance communication routers to support portability of MPI (Message-Passing Interface) based code to general-purpose and reconfigurable multicores. Development of an FPGA-based prototype (joint work, in 2005).