Students Advised by Prof. S.G. Ziavras

Ph.D. Dissertations

1.      William Christopher Contreras, “Robust, Efficient Structural Health Monitoring Using Wireless Sensor Networks,” 12/2017. Joined B. Braun Medical, Inc.

2.      Yaojie Lu, “Instruction Fusion and Vector Processor Virtualization for Higher Throughput Simultaneous Multithreaded Processors,” 5/2016. Joined Symbolic IO (Formulus Black).

3.      Seyed Amin Rooholamin, “Vector Processor Virtualization: Distributed Memory Hierarchy and Simultaneous Multithreading,” 5/2016. Joined Symbolic IO (Formulus Black).

4.      Spiridon Florin Beldianu, “Vector Coprocessor Sharing Techniques for Multicores: Performance and Energy Gains,” 5/2012. Joined Broadcom, San Jose, CA.

5.      Nitesh Guinde, “Hardware Support for Real-Time Network Security and Packet Classification using Field-Programmable Gate Arrays,” 4/2010. Currently Associate Professor, Goa College of Engineering, India.

6.      Sara Motahari, "Inference Prevention in Ubiquitous Social Computing," 12/2009, co-advisor. Joined Sprint Advance Analytics Lab, San Francisco area, CA. Currently with DOCOMO Innovations, Palo Alto, CA.

7.      Hongyan Yang, “Vector Support for Multi-Core Processor Chips with Major Emphasis on Configurable Multiprocessors," 2/2008. Currently with Qualcomm, San Diego, CA.

8.      Muhammad Zafrul Hasan, “Vector Customization and Reconfiguration Framework for Multi-kernel Embedded Applications,” 12/2007. Joined Texas A&M University, College Station as an Assistant Professor.

9.      Xin Tang, “Generalized Anomaly Detection Models for Malicious Executables," co-advisor, 12/2007. Macro-economy researcher & analyst of Investor Journal, Beijing, China.

10.  Xizhen Xu, "H-SIMD Machine: Configurable Parallel Computing for Data-Intensive Applications," 5/2006. Joined Integrated Device Technology, Inc. (IDT).

11.  Xiaofang Wang, "Design and Resource Management of Reconfigurable Multiprocessors for Data-Parallel Applications,'' Hashimoto Prize for AY05-06 ECE Best Dissertation, 12/2005. Joined Villanova University as an Assistant Professor. Currently Associate Professor.

12.  Dejiang Jin, "A Versatile Programming Model for Dynamic Load Balancing on Cluster Computers," 5/2005. Joined DataSynapse, Inc., Manhattan, NY; Grid Computing.

13.  Qian Wang, "A New-Generation Class of Parallel Architectures and their Performance Evaluation," 5/1999 (Computer Science Dept. student).

14.  Xi Li, "Investigation of Hybrid Message-Passing and Shared-Memory Architectures for Parallel Computers. A Case Study," 5/1995. Joined AT&T, NJ.

Graduate Visitors (from Other Universities), PostDocs & Visiting Scholars

1.       Huang Hao, Professor (University of International Business and Economics, Beijing).

2.       Christopher Dahlberg, Spring 2011, M.S. student (Jönköping University, Sweden). Master’s Thesis work done at the CAPPL Laboratory, NJIT. Thesis: “Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip”.

3.       Imtiaz Ahmed Sajid, 8/2009-2/2010, Ph.D. student (Pakistan).

4.       Cristina Rodríguez Sánchez, 9/2009-12/2009, Ph.D. student (Spain).

5.       Byoung-Il Kim, 7/2007-3/2009, PostDoc (Korea).

6.       Xizhen Xu, Summer 2006, PostDoc (NJIT graduate).

7.       Xiaofang Wang, Spring & Summer 2006, PostDoc (NJIT graduate).

8.       Dejiang Jin, Fall 2005, PostDoc (NJIT graduate).

 

M.S. Theses

1.      G.R. Sahu, “An Embedded System Supporting Dynamic Partial Reconfiguration of Hardware Resources for Morphological Image Processing,” Dec. 2014.

2.      G. Li, “High-Performance Matrix Multiplication on Intel and FPGA Platforms,” May 2012.

3.      T. Steele, “Design and Evaluation of an Adaptable Vector Coprocessor for Multicores,” May 2011.

4.      N. Al-Saber, "Kerberos Secure Phone Messenger," Dec. 2007.

5.      Q. Zhu, “Two Factor Authentication and Authorization with Ubiquitous Mobile Computing,” Dec. 2007.

6.      C.V.S. Nunez, “Development and Evaluation of a Simultaneous Multithreading Processor Simulator,” May 2007 (co-advisor).

7.      M. Kharaghesh, "FPGA-Based Implementation of Parallel Graph-Partitioning," May 2006.

8.      R. Bafna, “A Co-Processor Design to Support MPI Primitives in Configurable Multiprocessor Designs,” Dec. 2004.

9.       A. Sathe, “Configurable Computer Systems Can Support Dataflow Computing,” Dec. 2003.

10.   T. Kunta, "Design of an FPGA-Based Parallel SIMD Machine for Power-Flow Analysis,'' May 2003.

11.   S. Haridas, “FPGA Implementation of a Cholesky Algorithm for a Shared-Memory Multiprocessor Architecture,” May 2003.

12.   A.M. Sheth, “Sparse Matrix Product Implementation on FPGAs,” May 2003.

13.  S. Ingersoll,  "Emulation of the Data-Flow Computing Paradigm Using Field-Programmable Gate Arrays (FPGAs),'' Sept. 2000.  

14.  E.H. Staub, "Design, Implementation, and Evaluation of a Dual-Processor Shared-Memory Computer,'' Dec. 1998.

15.  J. Zydallis, "Communications Interfaces for the NJIT Point Design,'' Dec. 1997  (recipient of a von Karman Scholarship, U.S. Air Force).

16.  S. Krishnamurthy, "Evaluating the Communications Capabilities of the Generalized Hypercube Interconnection Network,''  Dec. 1997.

17.  A.O. Melkonian,  "Small Computer System Interface (SCSI) Universal Services for the TurboNet Parallel Computer,''    Jan. 1996.

18.  N.J. Lad, "Algorithms for the NJIT TurboNet Parallel Computer,''  Oct. 1995.

19.  R. Hross, "A Defect Detection Algorithm for Sequential and  Parallel Computers,''    May 1995.

20.  A. Mukherjee,  "Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduced Hypercube (RH) Parallel Computers,'' Aug. 1994.

21.  M.A. Sideras, "Investigation of Reduced Hypercube (RH) Networks: Embedding and Routing Capabilities,''  Dec. 1993.

22.  D.P. Shah,  "Multilevel Embeddings for Massively-Parallel Hypercubes,''  May 1993.

23.  B. Patel,  "Translation of Images on the Hypercube Using Leaf Codes,''  Dec. 1992.

24.   J.C. Liou, "Performance Analysis of Pyramid Mapping Algorithms,'' Dec. 1992.

25.  M.A. Siddiqui, "Comparing Techniques of Mapping Pyramid Algorithms onto the Hypercube: A  Case Study for the Connection Machine,''  May 1992.

26.  N.G. Haravu,  "Processor Allocation Strategies for Modified Hypercubes,'' May 1992.

27.  I. Shahid, "Connected Component Labelling on a Pair of Parallel Systems,''  May 1992.

28.  U.B. Iftikhar,  "Fast Arithmetic Operations on the Hypercube Using Conditional Sum Addition and  Modified Booth's Algorithm,'' Dec. 1991.

29.  A. Rana,  "Realization of High-Speed Carry Propagation Free Addition and Multiplication Using the Redundant Binary System on the Mesh  and Hypercube Connected Structures,'' December 1991.

30.   S.R. Bhatt,  "Efficient Hypercube Communications,'' Dec. 1991.

31.  S.C. Patel,  "Mapping Hierarchical Structures onto Hypercubes,''  Aug. 1991.

 

M.S. Projects

1.      Z. Zhao, “Image Segmentation Using K-Means Clustering on a Vector Coprocessor,” December 2014.

2.      D. Gomez, “Multicore Processing with Vector Acceleration Support on the FPGA-based ZedBoard with ARM Processors,” December 2013.

3.      S. Tong, “Design of a Scheduler in VHDL for Multicores with Shared Vector Units,” December 2013.

4.      J. Liu, “ZedBoard FPGA-based Development,” December 2013.

5.      M. Rahbar, “Image Segmentation on a Vector Processor,” December 2013.

6.      A. Ayyagari, “VHDL-based Design of a Crossbar Switch for Multicores,” December 2013.

7.      Y. Pang, “Vector Coprocessor Applications for Multicores,” May 2013.

8.      R. Vemagiri, “Embedded System Hardware-Software Infrastructure for Menu-based Ordering in Restaurants,” December 2012.

9.      S. Hamad, “Impact of USB and I/O Processor on Control System Communications,” May 2012.

10.  S. Suresh, “High-Performance, Low-Power Square-Root Design and Implementation for FPGAs,” May 2012.

11.  J. Chen, “FPGA-based Prototyping of Multiprocessors,” May 2012.

12.  A.M. Ravivarma, “Network On-Chip Optimization and Simulation,” May 2010.

13.  A. Hofmaier, “Pipelined Implementation of the Black-Scholes Equation for Options Trading Using FPGAs,” May 2009.

14.  J. Philip, "“Router Architecture for 2D-Mesh Network-on-Chip,” May 2008.

15.  S. Oberoi, "Kerberos Secure Phone Messenger," Dec. 2007.

16.  C.M. Nandikolla, “Developing Cluster-Based Analytical Server to Calculate Implied Volatility for Equity Derivative-Options,” Computer Science Dept., Dec. 2007.

17.  S.K. Pandit, “Streams-C Compiler for the Annapolis StarFire Multi-FPGA Board,” Aug. 2003.

18.  A. Marcose and M. Mellini, “Cracking the RSA Algorithm Using a Grid of Alpha Servers,” May 2003.

19.  Y. Zhang, “RS16 Microprocessor Implementation and Evaluation on the Altera Nios FPGA Development Board,” Dec. 2002.

20.  P. Kadari, “FPGA-Based Processor Porting,” Dec. 2002.

21.  Y. Han, "Multiprocessor (Multi-NIOS) Systems on FPGAs,'' Aug. 2002.

22.   L. Zisis, ''UML (Unified Modeling Language)-Based Integrated Early-Stage System Performance Evaluation,'' May 2002.

23.  J. Kopec, "VHDL Implementation of a Processing-In-Memory (PIM) Memory Chip for the Support of Dataflow Computation,'' Dec. 2001.

24.  M. Patel, "Shared-Memory Multiprocessor Architecture,'' May 2001.

25.  D. DiGiovanna, "Implementation of SCbus Clock Fallback in the Dialogic SpringWare Product Line,'' Dec. 1999.

26.  J. Patel, "VHDL Implementation and Evaluation of an Adaptable and Programmable Router for Parallel Computers,'' May 1999.

27.  T. Golota, "Design and Evaluation of an Adaptive Network Router for Very High-Performance,''  Dec. 1998.

28.  M. Kahn, "Material Identification Algorithms for Parallel Systems,'' Aug. 1994.

29.  A. Pavis, "Creating an Advanced Traveller's Information System Using a Geographical Information System,'' Dec. 1993.

30.  M.P. Khatri, "Binary Trees of Modified Hypercubes: A Family of Networks for Hypercube-Like Supercomputers,'' May 1993.

31.  J.A. Hosty, "PC-Based BLITZEN Simulator,'' Dec. 1992.

32.  S. Patel, "Efficient Simulation of Pyramids on Incomplete  Hypercubes,'' Aug. 1991.

 

Senior Projects

1.      J.A. Haluska, D. Bradford Jr. and Q.A. Hroub, “Hand Gesture Interface,” May 2010.

2.      N. Mahajan, E. Saro-Nunez and H. Tsang, “Versatile NoC Simulator,” May 2009.

3.      J. Kalwa, J. Duda and T. Price, “Power Optimization on a 32-bit ALU,” May 2008.

4.      A. George, “User location in SmartCampus based on system with locally defined coordinate system,” May 2008.

5.      J. Cameron, D. Ostrowski, M. Pooran and D, Scott, “Design of a Dual Core Encryption/Decryption Processor using the Advanced Encryption Standard (AES) Algorithm,” May 2008.

6.      J. Cutugno, T. Kalafut, D. Ehlers and M. Yalcinoz, “ASCO Power Technologies Network Test Unit,” co-advisement with ASCO Power Technologies, May 2007.

7.      A. Patel, S. Ammar , N. Siderias , A. Namit and  E.Y. Dollari, “ASCO Power Technologies Network Test Unit,” co-advisement with ASCO Power Technologies, May 2007.

8.       C. Comeau, B.G. Peyton and W. Wang, “ASCO Network Test Unit,” co-advisement with ASCO Power Technologies, May 2007.

9.      L. Banks, M. Patel, L. Ramic, A. Madisetty and A. Tomczak, “Instruction Level Parallelism: A VHDL Implementation,” co-advisement with IBM Poughkeepsie (NY), May 2004. (1st prize for a CoE senior project in Spring 2004.)

10.  A. Skoulariotis, F. Mohamood, J. Strapp, and Y. Demetriou, “Design of a Central Processing Unit,” co-advisement with IBM Poughkeepsie (NY), May 2003. (1st prize for an ECE senior project in Spring 2003.)

11.   K. Colon , T. Daly, H. Hifdi, and M. Zavliwala, “Hardwired Implementation of a 32 Instruction CPU with VLSI”, co-advisement with IBM Poughkeepsie (NY), Dec. 2002.

12.  P. Ferreira, G. Saldua, S. Hatley , M. Matos, and R. Day, "Micro-Sequenced Relatively Simple CPU (VLSI for Vertical Microcoding),” co-advisement with IBM Poughkeepsie (NY), Dec. 2002. (2nd prize  for an ECE senior project in Fall 2002.)

13.  S. Patel, S. Jadhav , R. Patel, and M. Patel, “VLSI Design and Simulation of a Relatively Simple CPU With a Micro-Sequenced Control Unit (Horizontal Microcoding),” co-advisement with IBM Poughkeepsie (NY), Dec. 2002.

14.  O. Amit, "VHDL Coding of a Programmable Network Router for Parallel Computers,'' May 2002.

15.  H. Sahera, "Simulation for a Universal, Dynamically Adaptable and  Programmable Network Router for Parallel Computers,'' May 2002. (Recipient of an NJ I-Tower award.)

16.  H. Januario, "Automated Light Sensing Drill Mechanism for High Accuracy,'' May 2000.

17.  S. Margo, "Very-Large-Instruction-Word (VLIW) CPU Design and Implementation,'' April 1997  (Honors program).

18.  W. Taraszkiewicz,  "Bicycle Computer,'' April 1997 (Honors program).

19.  J.S. Knapp, "Design and Manufacture of a DIMM Memory Module,'' March 1996.

20.  H. Elshazly, "Quartz Digital Clock,'' April 1995.  

21.  N. Antoniou, "Dual Intel 8085 Microprocessor System,'' April 1992.