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ECE459 Advanced Computer System Design Lab
Chapter 4
EXPERIMENT 4
CPU Design with Support for External Interrupts
4.1 Objective
The objective of this experiment is to design, simulate, and build a microcoded CPU capable of servicing external interrupt requests. Interrupts will be employed to initiate memory-mapped I/O. Firmware in the microcode will implement polling to determine the type of interrupt request.
The CPU implementation should use the Altera UP 1 Education Board. Onboard or additional push buttons should be used to initiate interrupts.
4.2 Introduction
execution unit which will contain the ALU, the registers, the 1-bit zero flag (Z), the 8-bit CPU address bus, and the 4-bit CPU data bus. The microcode unit to produce control signals. Finally, the I/O decode and interrupt unit.The system specifications follow:
The CPU will have three major sections. The
128 4-bit words of ROM starting at address 0 and 128 4-bit
words of RAM starting at address 128 (decimal). This arrangement will require
an 8-bit program counter (PC), an 8-bit memory-address register (MAR), a 4-bit
memory-data register (MDR), an 8-bit system address bus, and a 4-bit system
data bus.
The CPU should be able to access a minimum of two 4-bit
input ports (namely, IP0, IP1, IP2, and IP3) and an output port (OP0). A 4-bit interrupts-pending status register (IPEN)
also should be included to denote the type (in this case, ID number) of
pending interrupts.
The CPU should have a minimum of two program-addressable
4-bit registers: an Accumulator (AC) and a general-purpose Data Register (DR).
The 1-bit zero flag (Z) in the CPU will be set by
instructions as shown in Table 4.1.
The CPU should have
To support interrupts, a 1-bit interrupt-request
flag (IRQ)
and a 1-bit interrupt-enable flag (IEN) are needed. The CPU should
check for pending interrupts at the end of each instruction cycle. Pending
interrupts are never serviced by CPUs before complete execution of the current
instruction; otherwise, the information stored automatically when entering the ISR may not be complete to resume reliable execution of the user program.
When entering the ISR, the CPU should automatically save
the user program counter (PC) and the zero flag (Z). The PC and Z flag should be
automatically restored when returning from the ISR. The AC and DR must also be
saved in the beginning and restored at the end of the ISR.
The CPU instruction set is shown in the upper half of Table 4.1. Note that LOAD, STORE, and JUMPZ are 3-word instructions with a 4-bit opcode and an 8-bit address. NOP, MOVE, SUB, AND, and RETINT are 1-word instructions having just an opcode.
Instructions | Operations |
NOP | none |
LOAD $XX | AC ← M [$XX]. Set Z=1 if AC = 0, else Z=0 |
STORE $XX | M [$XX] ← AC |
MOVE | DR ← AC |
SUB | AC ← AC - DR. Set Z=1 if AC = 0, else Z=0 |
AND | AC ← AC AND DR. Set Z=1 if AC = 0, else Z=0 |
JUMPZ $XX | If Z = 1 then PC ← $XX |
RETINT | Return from ISR. Restore PC and Z flag. Enable interrupts |
Optional Instructions | Operations |
SWAP ANDI $X SUBI $X LOADI $X TESTI $X |
AC ↔ DR. Set Z=1 if AC = 0, else Z=0 AC ← AC AND $X. Set Z=1 if AC = 0, else Z=0 AC ← AC - $X. Set Z=1 if AC = 0, else Z=0 AC ← $X. Set Z=1 if AC = 0, else Z=0 Set Z=1 if AC = $X, else Z=0 |
extra credit are listed in the lower half of Table 4.1. These include 1-word and 2-word instructions. These instructions can be implemented with very little or no additional hardware in the execution unit.
Optional instructions for
Hardware to support three or four different interrupts.
The action taken by the ISR depends each time on the type of interrupt. All possible actions are described in Table 4.2.
Table 4.2. Interrupt service routine (ISR) actions. |
|
Interrupt | Action |
A | Output the value of memory location $F4 to the 4-bit LEDs (i.e., OP0) |
B | Input a 4-bit value from input port IP0 and write that data to location $F5 in memory |
C | Input the low-order nibble of a memory address from input port IP1 and output the data at that location to output port OP0. Assume that the high-order nibble of the address is $F |
Optional | Action |
D | Input an 8-bit memory address from input ports IP2 and IP3 and output the data at that location to output port OP0. If interrupt D is implemented, interrupt C is optional. Both may be implemented for extra credit. |
4.4 Experiment
Pre-Lab Assignment
Design the above CPU in block diagram form. Write the microcode. Design the hardware which is external to the CPU.
Lab AssignmentUse Max+PLUS II to implement and simulate your design for the set of required instructions. For extra credit, your code also should demonstrate the optional features of the CPU.
Demonstrate the simulator and the hardware implementation to the instructor.
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