SCALABLE ARCHITECTURES FOR LOW COST, HIGH PERFORMANCE PARALLEL COMPUTING

Sotirios G. Ziavras

It was emphasized in "Contribution 1" that the hypercube interconnection network has very high VLSI complexity that does not permit the construction of high performance, massively parallel systems. This reason motivated my work on reduced hypercube (RH) interconnection networks that have lower VLSI complexity than hypercubes and yield comparable throughput.

 A similar motivation is behind the introduction of the family of reconfigurable generalized hypercube (RGH) architectures for the interconnection of processors in parallel computers. My motivation for the introduction of the RGH architectures was to reduce the generalized hypercube's high VLSI complexity, while maintaining to a large extent its outstanding performance. For systems with the same number of processors, generalized hypercubes yield much higher throughput than the very popular families of conventional hypercubes and $k$-ary $n$-cubes. However, generalized hypercubes have dramatically higher VLSI complexity than the latter pair of interconnection networks. Therefore, generalized hypercube systems have never been constructed.

 The one-dimensional building block of the proposed family of RGHs has diameter equal to only two and contains a scalable mesh of very simple programmable switches for the interconnection of processors. This mesh of switches has lower VLSI complexity than a crossbar of the same size and supports the implementation in a single communication step of any direct connection found in the conventional hypercube with the same number of processors. Larger systems are produced by repeating the same structure (i.e., the building block) in multiple dimensions. The scalability of these systems is a great asset.

 For important classes of frequently used application algorithms, such as algorithms that apply ascend-descend operations, any RGH can achieve performance comparable to that of the generalized hypercube with the same number of processors. The low VLSI complexity of RGHs permits the construction of very powerful, massively parallel systems.

 Extensive comparison of the cost for the aforementioned systems has been carried out. The hardware cost of RGHs was shown to be even lower than that of the very popular fat tree, an interconnection network present in the Connection Machine system CM-5 supercomputer. Therefore, RGHs are viable candidates for the construction of versatile, scalable parallel computers.


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Last updated 11/02/98, SGZ