SEGREEN INGERSOLL and SOTIRIOS G. ZIAVRAS
Abstract
This paper presents a new design that implements the data-driven (i.e.
dataflow) computation paradigm with intelligent memories. Also, a relevant
prototype that employs FPGAs is presented for the support of intelligent
memory structures. Instead of giving the CPU the privileged right to decide
what instructions to fetch in each cycle (as is the case for control-flow
CPUs), instructions in dataflow computers enter the execution unit on their
own when they are ready to execute. This way, the application-knowledgeable
algorithm, rather than the application-ignorant CPU, is in control. This
approach could eventually result in outstanding performance and elimination
of large numbers of redundant operations that plague current control-flow
designs. Control-flow and dataflow machines are two extreme computation
paradigms. In their pure form, the former machines follow an inherently
sequential execution process while the latter are parallel in nature. The
sequential nature of control-flow machines makes them relatively easy to
implement compared to dataflow machines, which have to address a number
of issues that are easily solved in the realm of the control-flow paradigm.
Our dataflow design solves these issues at the intelligent memory level,
separating the processor from dataflow maintenance tasks. It is shown that
using intelligent memories with basic components similar to those of FPGAs
produces a feasible approach. Expected improvements within the next few
years in underlying intelligent memory and FPGA technologies will
have the potential to make the effect of our approach even more dramatic.
Keywords: dataflow computation, field-programmable gate arrays
(FPGAs), prototyping, intelligent memories.
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