.NJITElectrical and Computer Engineering Department

 

Sotirios G. Ziavras
Professor

 

Contact | Classes | CV | Research | Publications |


Click here for a single list of selected publications from all research areas of interest.

 

Selected Publications (by Research Area)

Follow the links to download papers

 

 

1.     HIGH-PERFORMANCE  EMBEDDED COMPUTING, including SoCs (SYSTEMS-ON-CHIP) .

HIGH-PERFORMANCE HETEROGENEOUS MULTI-CORES, including ACCELERATORS, and Runtime Resource and Energy Management.

HIGH-PERFORMANCE RECONFIGURABLE COMPUTING, including Runtime Resource and Energy Management.

FPGA-BASED IMPLEMENTATIONS AND SYSTEM PROTOTYPING.

·         W. Contreras and S.G. Ziavras, “Low-cost, Efficient Output-only Infrastructure Damage Detection with Wireless Sensor Networks,” IEEE Transactions on Systems, Man, and Cybernetics: Systems, 2017.

·         W.C. Contreras and S.G. Ziavras, “Efficient Infrastructure Damage Detection and Localization Using Wireless Sensor Networks, with Cluster Generation for Monitoring Damage Progression,” 8th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, October 2017.

·         W.C. Contreras and S.G. Ziavras, “Efficient Structural Health Monitoring with Wireless Sensor Networks using a Vibration-Based Frequency Domain Pattern Matching Technique,” 8th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, October 2017.

·         Y. Lu and S.G. Ziavras, “Instruction Fusion for Multiscalar and Many-Core Processors,” International Journal of Parallel Programming, Vol. 45, No. 1,  2017, pp. 67-78, DOI: 10.1007/s10766-015-0386-1.

·         W. Contreras and S.G. Ziavras, “Wireless Sensor Network-based Infrastructure Damage Detection Constrained by Energy Consumption,” The 7th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, October 2016.

·         Y. Lu, S. Rooholamin and S.G. Ziavras, “Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration,” IEEE Computer Society Annual Symposium on VLSI, July 2016.

·         Y. Lu, S. Rooholamin and S.G. Ziavras, “Vector Coprocessor Virtualization for Simultaneous Multithreading,” ACM Transactions on Embedded Computing Systems, Vol. 15, No. 3, May 2016, pp. 57:1-57:25 (DOI 10.1145/2898364).

·         W.C. Contreras and S.G. Ziavras, “A Wireless Sensor Network-based Pattern Matching Technique for the Circumvention of Environmental and Stimuli-related Variability in Structural Health Monitoring,” IET Wireless Sensor Systems, Vol. 6, No. 1, 2016, pp. 26-33 (DOI 10.1049/iet-wss.2014.0090).

·         S.A. Rooholamin and S.G. Ziavras, “Modular Vector Processor Architecture Targeting at Data-Level Parallelism,” Microprocessors and Microsystems (Elsevier journal), Vol. 39, No. 4, June 2015, pp. 237-249 (DOI: 10.1016/j.micpro.2015.04.007).

·         S.F. Beldianu and S.G. Ziavras, “Performance-Energy Optimizations for Shared Vector Accelerators in Multicores,” IEEE Transactions on Computers, Vol. 64, No. 3, March 2015, pp. 805-817 (DOI:10.1109/TC.2013.2295820).

·         S.F. Beldianu and S.G. Ziavras, “ASIC Design of Shared Vector Accelerators for Multicore Processors,” The 26th International Symposium on Computer Architecture and High Performance Computing, October 2014.

·         S.F. Beldianu and S.G. Ziavras, “Multicore-based Vector Coprocessor Sharing for Performance and Energy Gains,” ACM Transactions on Embedded Computing Systems, Special Issue on Application Specific Processors, Vol. 13, No. 2, September 2013, pp. 17:1-17:25 (acceptance: 15.15%).

·         S. Suresh, S.F. Beldianu and S.G. Ziavras, “FPGA and ASIC Square Root Designs for High Performance and Power Efficiency,” 24th IEEE International Conference on Application-specific Systems, Architectures and Processors, June 2013.

·         N.B. Guinde, R. Rojas-Cessa and S.G. Ziavras, “Packet Classification using Rule Caching,” 4th International Conference on Information, Intelligence, Systems and Applications, Special Session on Multimedia and Smart Applications, July 2013.  

·         S.F. Beldianu, C. Dahlberg, T. Steele and S.G. Ziavras, “Versatile Design of Shared Vector Coprocessors for Multicores,” Microprocessors and Microsystems , Vol. 36, 2012, pp. 543–554.

·         I. Sajid, M.M. Ahmed and S.G. Ziavras, “Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm,” Journal of Signal Processing Systems, Vol. 67, No. 2, May 2012, pp. 157-166.

·         S.F. Beldianu and S.G. Ziavras, “On-Chip Vector Coprocessor Sharing for Multicores,” 19th Euromicro International Conference on Parallel, Distributed and Network-Based Computing, February 2011, pp. 431-438.

·         N.B. Guinde, S.G. Ziavras and R. Rojas-Cessa, “Efficient Packet Classification on FPGAs also Targeting at Manageable Memory Consumption,” 4th International Conference on Signal Processing and Communication Systems, December 2010, 10 pages.

·         N.B. Guinde and S.G. Ziavras, “Efficient Hardware Support for Pattern Matching in Network Intrusion Detection,” Computers and Security (The official journal of Technical Committee 11 (computer security) of the International Federation of Information Processing), Volume 29, No. 7, October 2010, pp. 756-769.

·         I. Sajid, S.G. Ziavras and M.M Ahmed, “Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance,” 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, September 2010, pp. 763-770.

·         M. Hasan, T. Davis, T. Kensinger and S. Ziavras, “Framework Improvement for Multi-module Embedded Reconfigurable Systems,” IEEE Symposium on Field-Programmable Custom Computing Machines, May 2010.

·         I. Sajid, S.G. Ziavras and M.M. Ahmed, FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization,” International Conference on Computer Vision Theory and Applications, May 2010, pp. 227-232.

·         N.B. Guinde and S.G. Ziavras, “Novel FPGA-Based Signature Matching for Deep Packet Inspection,” 4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, April 2010 (Lecture Notes in Computer Science, Springer Subseries on Security and Cryptology, Vol. 6033).

·         M.Z. Hasan and S.G. Ziavras, “Customized Kernel Execution on Reconfigurable Hardware for Embedded Applications," Embedded Hardware Design, Microprocessors and Microsystems, Vol. 33, No. 3, May 2009, pp. 211-220.

·         B.-I. Kim and S.G. Ziavras, "Low-Power Multiplierless DCT for Image/Video Coders," 13th IEEE International Symposium on Consumer Electronics, Mielparque-Kyoto, Kyoto, Japan, May 25-28, 2009, pp. 133-136.

·         X. Wang and S.G. Ziavras, "A Multiprocessor-on-a-Programmable-Chip Reconfigurable System for Matrix Operations with Power-Grid Case Studies," International Journal of Computational Science and Engineering, Special Issue on Parallel and Distributed Scientific and Engineering Computing,  in print. 

·         N. Guinde and S.G. Ziavras, “An Adaptable Platform for Network Intrusion Detection Systems,” 8th New Jersey Universities Homeland Security Research Consortium Symposium  on Homeland Security, Princeton University, New Jersey, Dec. 5, 2008 (poster).

·         M.Z. Hasan and S.G. Ziavras, "Reconfiguration Framework for Multi-kernel Embedded Applications," 2nd Annual Reconfigurable and Adaptive Architectures Workshop (in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture), Chicago, Illinois, December 2007.

·         S.G. Ziavras, A. Gerbessiotis and R. Bafna, "Coprocessor Design to Support MPI Primitives in Configurable Multiprocessors," Integration, the VLSI Journal , Vol. 40, No.3, 2007, pp. 235-252.

·         H. Yang, S.G. Ziavras and J. Hu, "Reconfiguration Support for Vector Operations,"  International Journal of High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 89 - 97.

·         X. Wang and S.G. Ziavras, “Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors,” 8th IEEE International Symposium on Quality Electronic Design (ISQED),  San Jose, California, March 26-28, 2007, pp. 386-391.

·         M.Z. Hasan and S.G. Ziavras, "Resource Management for Dynamically-Challenged Reconfigurable Systems," 12th IEEE Conference on Emerging Technologies and Factory Automation, 2007, pp. 119-126.

·         X. Wang, S.G. Ziavras and J. Hu, “Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors,” International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, June 25-28, 2007.

·         H. Yang, S. Wang, S.G. Ziavras and J. Hu, “Vector Processing Support for FPGA-Oriented High Performance Applications,” IEEE Computer Society Annual Symposium on VLSI, May 9-11, 2007.

·         X. Wang, S.G. Ziavras, et al,  “Parallel Solution of Newton’s Power Flow Equations on Configurable Chips,” International Journal of Electrical Power and Energy Systems, Vol. 29, No. 5, June 2007, pp. 422-431.

·         X. Wang, S. G. Ziavras and J. Hu, “System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors,” IEEE International Conference on Computer Design, San Jose, California, October 1-4, 2006.

·         X. Wang and S.G. Ziavras, "Exploiting Mixed-Mode Parallelism for Matrix Operations on the HERA Architecture through Reconfiguration," IEE Proceedings Computers and Digital Techniques, Vol. 153, No. 4, July 2006, pp. 249-260.

·         X. Xu and S.G. Ziavras, "A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers," IEICE Transactions on Information and Systems, Special Issue on Parallel/Distributed Computing and Networking, Vol. E89-D, No. 2, February 2006, pp. 639-646.

·         X. Wang and S.G. Ziavras, “A Framework for Dynamic Resource Management and Scheduling on Reconfigurable Mixed-Mode  Multiprocessors,” IEEE International Conference on Field-Programmable Technology , Singapore, Dec. 11-14, 2005.

·         X. Xu, S.G. Ziavras, and T.-G. Chang, “An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method,” IFIP International Conference on Embedded and Ubiquitous Computing, Nagasaki, Japan, Dec. 6-9, 2005 .

·         X. Wang and S.G. Ziavras, “Adaptive Scheduling of Array-Intensive Applications on Mixed-Mode Reconfigurable Multiprocessors,” 39th IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, Oct. 30—Nov. 2, 2005.

·         X. Xu and S.G. Ziavras, “A Hierarchically-Controlled SIMD Machine for 2D DCT on FPGAs,” IEEE International Systems-On-Chip Conference, Washington, D.C., Sept. 25-28, 2005.

·         H. Yang and S.G. Ziavras, “FPGA-Based Vector Processor for Algebraic Equation Solvers,” IEEE International Systems-On-Chip Conference, Washington, D.C., Sept. 25-28, 2005.

·         X. Xu and S.G. Ziavras, “H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication,” IEEE International Conference on Computer Design, San Jose , California , Oct. 2-5, 2005.

·         M.Z. Hasan and S.G. Ziavras, “FPGA-Based Vector Processing for Solving Sparse Sets of Equations,” IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 17-20, 2005.

·         S.G. Ziavras, X. Wang and M.Z. Hasan, “Intra- and Inter-FPGA Programmable Multiprocessor Designs with Emphasis on Large Scale Matrix Operations,” 1st Workshop on Architecture Research using FPGA Platforms, (in conjunction with the 11th High Performance Computer Architecture Symposium), San Francisco, Febr. 13, 2005.

·         S.G. Haridas and S.G. Ziavras, "FPGA Implementation of a Cholesky Algorithm for a Shared-Memory  Multiprocessor Architecture," Parallel Algorithms and Applications, Vol. 19, No. 4, December 2004, pp. 211-226.

·         X. Wang and S.G. Ziavras, "Parallel LU Factorization of Sparse Matrices on FPGA-Based Configurable Computing Engines," Concurrency and Computation: Practice and Experience , Vol. 16, No. 4, April 2004, pp. 319-343.

·         X. Wang and S.G. Ziavras, "Mixed-Mode Scheduling for Parallel LU Factorization of Sparse Matrices on the Reconfigurable HERA Computer," Advances in Computer Science and Technology, St. Thomas, U.S. Virgin Islands, November 22-24, 2004.

·         X. Wang and S.G. Ziavras, "HERA: A Reconfigurable and Mixed-Mode Parallel Computing Engine on Platform FPGAs," Parallel and Distributed Computing and Systems, Boston, Massachusetts, November 9-11, 2004.

·         X. Wang and S.G. Ziavras, "A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization ," 5th International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC-2004), in conjunction with The 18th International Parallel and Distributed Processing Symposium (IPDPS-2004), April 26-30, Santa Fe, New Mexico.

·         X. Wang and S.G. Ziavras, "Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations ," IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, December 15-17, 2003.

·         X. Wang and S.G. Ziavras, "Parallel Direct Solution of Linear Eqautions on FPGA-Based Machines," 11th International  Conference on Parallel and Distributed Real-Time Systems, Nice, France, April 22-23, 2003.

·         X. Wang, S.G. Ziavras, and J. Savir, "Efficient LU Factorization on FPGA-Based Machines," 7th International Multi-Conference on  Power and Energy Systems, Palm Springs, California, February 24-26, 2003.

·         S.G. Ziavras, ``Connected Component Labelling on the BLITZEN Massively Parallel Processor,'' Image and Vision Computing, Vol. 11, No. 10, Dec. 1993, pp. 665-668.

 

2.     PARALLEL PROCESSING: APPLICATIONS & SYSTEMS

SUPERCOMPUTING TECHNIQUES

TASK SCHEDULING   &  APPLICATION MAPPING

·         D. Jin and S.G. Ziavras, "Robust Scalability Analysis and SPM Case Studies," The Journal of Supercomputing, Vol. 43, No. 3, March 2008, pp. 199-223.

·         D. Jin and S.G. Ziavras, "Modeling Distributed Data Representation and its Effect on Parallel Data Accesses," Journal of Parallel and Distributed Computing, Special Issue on Design and  Performance of Networks for Super-, Cluster-, and Grid-Computing, Vol. 65, No. 10, October 2005, pp. 1281-1289.

·         D. Jin and S.G. Ziavras, "A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters," IEEE Transactions on Parallel and Distributed Systems, Vol. 15, No. 9, September 2004, pp. 783-794.

·         D. Jin and S.G. Ziavras, "A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters," IEICE Transactions on Information and Systems, Special Issue on Hardware/Software Support for High Performance Scientific and Engineering Computing, Vol. E87-D, No. 7, July 2004, pp. 1774-1781.

·         D. Jin and S.G. Ziavras, "A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters ," 2nd Workshop on Hardware/Software Support for High performance Scientific and Engineering Computing (SHPSEC-03) [in conjunction with the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT-03)], New Orleans, Louisiana, Sep. 27--Oct. 1, 2003.

·         D. Jin and S.G. Ziavras, "Load Balancing on PC Clusters with the Super-Programming Model," Workshop on Compile/Runtime Techniques for Parallel Computing (in conjunction with the International Conference on Parallel Processing-ICPP03),  Kaohsiung, Taiwan, October 6-9, 2003.

·         S.G. Ziavras and M.A. Sideras, ``Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers,'' International Journal of Pattern Recognition and Artificial Intelligence, Special Issue on Parallel Image Analysis, Theory and Applications, Vol. 9, No. 4, August 1995, pp. 679-698.

·         S.G. Ziavras and P. Meer, ``Adaptive Multiresolution Structures for Image Processing on Parallel Computers,'' Journal of Parallel and Distributed Computing), Vol. 23, No. 3, Dec. 1994, pp. 475-483.

·         S.G. Ziavras and N.G. Haravu, "Processor Allocation Strategies for Modified Hypercubes," IEE Proceedings E: Computers and Digital Techniques, May 1994, pp. 196-204.

·         S.G. Ziavras and D.P. Shah, ``High-Performance Emulation of Hierarchical Structures on Hypercube Supercomputers,'' Concurrency: Practice and Experience, Vol. 6, No. 2, April 1994, pp. 85-100.

·         S.G. Ziavras and D.P. Shah, ``Efficient Implementation of Multilevel Algorithms on Hypercube Supercomputers for Computer Vision,'' Workshop on Computer Architectures for Machine Perception '93 (CAMP'93), New Orleans, Louisiana, Dec. 15-17, 1993, pp. 313-322.

·         S.G. Ziavras, ``Efficient Mapping Algorithms for a Class of Hierarchical Systems,'' IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 11, Nov. 1993, pp. 1230-1245.

·         S.G. Ziavras and M.A. Siddiqui, ``Pyramid Mappings onto Hypercubes for Computer Vision: Connection Machine Comparative Study,'' Concurrency: Practice and Experience, Vol. 5, No. 6, Sept. 1993, pp. 471-489.

·         S.G. Ziavras, "Mapping Single and Multiple Multilevel Structures onto the Hypercube," IEE Proceedings E: Computers and Digital Techniques, Vol. 140, No. 2, March 1993, pp. 115-118.

·         S.G. Ziavras, ``Connection Machine Results for Pyramid Embedding Algorithms,'' Lecture Notes in Computer Science, L. Bouge, M. Cosnard, Y. Robert, D. Trystram (Eds.), Vol. 634, Springer-Verlag, 1992, pp. 31-36.

·         N.G. Haravu and S.G. Ziavras, ``Processor Allocation for a Class of Hypercube-Like Supercomputers,'' Supercomputing '92, Minneapolis, Minnesota, Nov. 16-20, 1992, pp. 740-749.

·         S.G. Ziavras, ``Embedding Multilevel Structures into Massively Parallel Hypercubes - Connection Machine Results for Computer Vision Algorithms,'' 4th Symposium on the Frontiers of Massively Parallel Computation, McLean, Virginia, Oct. 19-21, 1992, pp. 586-589.

·         S.G. Ziavras, ``Connection Machine Results for Pyramid Computations,'' Supercomputing Symposium '92, Montreal, Canada, June 7-10, 1992, pp. 296-316.

·         S.C. Patel and S.G. Ziavras, ``Comparative Analysis of Techniques that Map Hierarchical Structures into Hypercubes,'' International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., Oct. 8-11, 1991, pp. 295-299.

·         S.G. Ziavras, ``High Performance Mapping for Massively Parallel Hierarchical Structures,'' 3rd Symposium on the Frontiers of Massively Parallel Computation, College Park, Maryland, Oct. 8-10, 1990, pp. 251-254.

·         S.G. Ziavras, ``Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems,'' International Conference on Parallel Processing, St. Charles, Chicago, Illinois, Aug. 13-17, 1990, pp. 226-233.

·         S.G. Ziavras, ``On the Mapping Problem for Multi-Level Systems,'' ACM/IEEE Conference on Supercomputing, Reno, Nevada, Nov. 12-17, 1989, pp. 399-408.

·         L.S. Davis, D. DeMenthon, T. Bestul, D. Harwood, H.V. Srinivasan and S. Ziavras, "RAMBO - Vision and Planning on the Connection Machine," DARPA Image Understanding Workshop, Palo Alto, California, May 23-26, 1989, pp. 631-639.

·         L.S. Davis, D. DeMenthon, T. Bestul, S. Ziavras, H.V. Srinivasan, M. Siddalingaiah and D. Harwood, "Robot Acting on Moving Bodies (RAMBO): Preliminary Results," NASA Goddard Conference on Space Applications of Artificial Intelligence, NASA Goddard Space Flight Center, Greenbelt, Maryland, May 16-17, 1989, pp. 223-236.

·         L.S. Davis, D. DeMenthon, T. Bestul, S. Ziavras, H.V. Srinivasan, M. Siddalingaiah and D. Harwood, "Robot Acting on Moving Bodies (RAMBO): Interaction with Tumbling Objects," NASA Conference on Space Telerobotics, Jet Propulsion Lab., Caltech, Pasadena, California, Jan. 31-Feb. 2, 1989, Vol. 1, pp. 251-260.

·         S.G. Ziavras and L.S. Davis, ``Fast Addition on the Fat Pyramid and its Simulation on the Connection Machine,'' From Pixels to Features, J.C. Simon (Ed.), Elsevier Science, 1989, pp. 373-382.

·         E.V. Krishnamurthy and S.G. Ziavras, ``Multivariable Spline-Blending Approximation on the Connection Machine,'' Center for Automation Research and Computer Science Department, University of Maryland, College Park, Technical Report CAR-TR-402 and CS-TR-2132, 1988.

·         E.V. Krishnamurthy and S.G. Ziavras, ``Grid Evaluation-Interpolation on the Connection Machine Using Tensor Products and g-Inversion,'' Center for Automation Research and Computer Science Department, University of Maryland, College Park, Technical Report CAR-TR-401 and CS-TR-2127, 1988.

·         E.V. Krishnamurthy and S.G. Ziavras, ``Complexity of Matrix Partitioning Schemes for g-Inversion on the Connection Machine,'' Center for Automation Research and Computer Science Department, University of Maryland, College Park, Technical Report CAR-TR-400 and CS-TR-2126, 1988.

·         E.V. Krishnamurthy and S.G. Ziavras, ``Matrix g-Inversion on the Connection Machine,'' Center for Automation Research and Computer Science Department, University of Maryland, College Park, Technical Report CAR-TR-399 and CS-TR-2125, 1988.

·         S.G. Ziavras and N.A. Alexandridis, ``Multigranularity Hierarchical Image Transform Architecture,'' 3rd International Conference on Supercomputing, Boston, Massachusetts, May 15-20, 1988, pp. 118-127.

 

3.     HIGH-PERFORMANCE INTERCONNECTION NETWORKS

HIGH-PERFORMANCE COMPUTER ARCHITECTURE

ROUTER DESIGN

HIGH-PERFORMANCE VECTOR PROCESSING

·         S.F. Beldianu and S.G. Ziavras, “Multicore-based Vector Coprocessor Sharing for Performance and Energy Gains,” ACM Transactions on Embedded Computing Systems, Accepted for publication.

·         S.F. Beldianu, C. Dahlberg, T. Steele and S.G. Ziavras, “Versatile Design of Shared Vector Coprocessors for Multicores,” Microprocessors and Microsystems: Embedded Hardware Design  (Elsevier journal), Accepted for publication.

·         S. Wang, J. Hu and S.G. Ziavras, “Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, April 2012, pp. 643-654.

·         I. Sajid, M.M. Ahmed and S.G. Ziavras, “Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm,” Journal of Signal Processing Systems, accepted for publication.

·         S. Wang, J. Hu and S.G. Ziavras, “Exploring BTB Access Filtering for Low-Energy and High-Performance Microarchitectures,” IET Computers & Digital Techniques, Vol. 6, No. 1, January 2012.

·         S.F. Beldianu and S.G. Ziavras, “On-Chip Vector Coprocessor Sharing for Multicores,” 19th Euromicro International Conference on Parallel, Distributed and Network-Based Computing, February 2011.

·         S.F. Beldianu, R. Rojas-Cessa, E. Oki and S.G. Ziavras, “Scheduling for Input-Queued Packet Switches by a Re-configurable Parallel Match Evaluator,” IEEE Communications Letters, , Vol. 14, No. 4, April 2010, pp. 357-359.

·         S. Beldianu, R. Rojas-Cessa, E. Oki and S.G. Ziavras, “Re-configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches,” 18th IEEE International Conference on Computer Communications and Networks, San Francisco, California, August 2–6, 2009.

·         S. Wang, J. Hu and S.G. Ziavras, “On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors,” IEEE Transactions on Computers, Vol. 58, No. 9, September 2009, pp. 1171-1184.

·         J. Hu, S. Wang and S.G. Ziavras, “On the Exploitation of Narrow-Width Values for Improving Register File Reliability,” IEEE Transactions on VLSI Systems, Vol. 17, No. 7, July 2009, pp. 953-963.

·         B.-I. Kim and S.G. Ziavras, "Low-Power Multiplierless DCT for Image/Video Coders," 13th IEEE International Symposium on Consumer Electronics, Mielparque, Kyoto, Japan, May 25-28, 2009.

·         M.Z. Hasan and S.G. Ziavras, “Customized Kernel Execution on Reconfigurable Hardware for Embedded Applications," Embedded Hardware Design, Microprocessors and Microsystems, Vol. 33, No. 3, May 2009, pp. 211-220.

·         S. Wang, J. Hu and S.G. Ziavras, “Self-Adaptive Data Caches for Soft-Error Reliability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 8, August 2008, pp. 1503-1507.

·         N.A. Al-Saber, S. Oberoi, R. Rojas-Cessa and S.G. Ziavras, “Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling,” IEEE Sarnoff Symposium, Princeton, New Jersey, April 28-30, 2008.

·         S. Wang, J. Hu and S.G. Ziavras, “BTB Access Filtering: A Low Energy and High Performance Design,” IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, 2008.

·         M.Z. Hasan and S.G. Ziavras, "Reconfiguration Framework for Multi-kernel Embedded Applications," 2nd Annual Reconfigurable and Adaptive Architectures Workshop (in conjunction with the 40th Annual IEEE/ACM International Symposium on Microarchitecture), Chicago, Illinois, December 2007.

·         H. Yang, S.G. Ziavras and J. Hu, "Reconfiguration Support for Vector Operations,"  International Journal of High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 89 - 97.

·         S. Wang, H. Yang, J. Hu and S.G. Ziavras, “Asymmetrically Banked Value-Aware Register Files,” IEEE Computer Society Annual Symposium on VLSI, May 9-11, 2007.

·         H. Yang, S. Wang, S.G. Ziavras and J. Hu, “Vector Processing Support for FPGA-Oriented High Performance Applications,” IEEE Computer Society Annual Symposium on VLSI, May 9-11, 2007.

·         S. Wang, J. Hu and S.G. Ziavras, “On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors,” 6th Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, July 17 - 20, 2006, pp. 14-20.

·         J. Hu, S. Wang and S.G. Ziavras, “In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability,” IEEE International Conference on Dependable Systems and Networks, Philadelphia, Pennsylvania, June 25-28, 2006, pp. 281-290.

·         J. S. Hu, G. M. Link, J. K. John, S. Wang and S. G. Ziavras, "Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures," 10th Asia-Pacific Computer Systems Architecture Conference, Singapore, October 24-26, 2005.

·         J.K. John, J.S. Hu and S.G. Ziavras, “Optimizing the Thermal Behavior of Subarrayed Data Caches,” IEEE International Conference on Computer Design , San Jose , California , Oct. 2-5, 2005 .

·         S.G. Ziavras, "History of Computation," The Encyclopedia of Life Support Systems, Developed under the Auspices of the UNESCO (United Nations Educational, Scientific and Cultural Organization), Eolss Publishers, Oxford, United Kingdom, Theme 6.45: Computer Science and Engineering, 2002 (nominated). Also available at http:// www.eolss.net, 2004.

·         S.G. Ziavras, "Computer Systems," The Encyclopedia of Life Support Systems, Developed under the Auspices of the UNESCO, Eolss Publishers, Oxford, United Kingdom, Theme 6.45: Computer Science and Engineering, 2002 (nominated). Also available at http:// www.eolss.net, 2004.   

·         S.G. Ziavras, "Processor Design Based on Dataflow Concurrency," Microprocessors and Microsystems, Vol. 27, No. 4, May 2003, pp. 199-220.

·         S.G. Ziavras, Q. Wang, and P. Papathanasiou, "Viable Architectures for High-Performance Computing," The Computer Journal, Vol. 46, No. 1, 2003, pp. 36-54.

·         S. Ingersoll and S.G. Ziavras, "Dataflow  Computation  with  Intelligent  Memories Emulated on Field-Programmable Gate  Arrays (FPGAs)," Microprocessors and Microsystems , MICRO2002.pdf , Vol. 26, No.  6,  August 2002,  pp. 263-280.

·         T. Golota and S.G. Ziavras, ``A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers,'' VLSI Design (abstract), VLSIdesign.pdf, Vol. 12, No. 1, 2001, pp. 25-52.

·         S.G. Ziavras, H. Grebel, A.T. Chronopoulos, and F. Marcelli, ``A New-Generation Parallel Computer and its Performance Evaluation,'' Future Generation Computer Systems(abstract), FGCS.pdf, Vol. 17, No. 3, December 2000, pp. 315-333.

·         S.G. Ziavras and Q. Wang, ``Robust Interprocessor Connections for Very-High performance,'' Robust Communication Networks: Interconnection and Survivability, N. Dean, F. Hsu, and R. Ravi (Eds.), American Mathematical Society, 2000, pp. 143-167.

·         S.G. Ziavras, ``Versatile Processor Design for Efficiency and High Performance,'' International Symposium on Parallel Architectures, Algorithms, and Networks, Dallas, Texas, December 7-9, 2000, pp. 266-271. ISPAN2000.pdf 

·         T. Golota and S.G. Ziavras, ``A Versatile Router for High-Performance Computing,'' International Conference on Parallel and Distributed Computing and Systems, MIT, Massachusetts, Nov. 3-6, 1999, pp. 738-743.

·         S.G. Ziavras, Q. Wang, N. Alexandridis, and P. Papathanasiou, ``Cost and Performance Analysis of Scalable Parallel Architectures,'' International Conference on Parallel and Distributed Computing and Systems, MIT, Massachusetts, Nov. 3-6, 1999, pp. 113-118.

·         Q. Wang and S.G. Ziavras, ``Powerful and Feasible Processor Interconnections with an Evaluation of Their Communications Capabilities,'' International Symposium on Parallel Architectures, Algorithms and Networks, Freemantle, Australia, June 23-25, 1999, pp. 222-227.

·         S.G. Ziavras and S. Krishnamurthy, ``Evaluating the Communications Capabilities of the Generalized Hypercube Interconnection Network,'' Concurrency: Practice and Experience, Vol. 11, No. 6, May 1999, pp. 281-300.

·         S.G. Ziavras, ``Investigation of Various Mesh Architectures with Broadcast Buses for High Performance Computing,'' VLSI Design, Special Issue on High Performance Bus-Based Architectures, Vol. 9, No. 1, January 1999, pp. 29-54.

·         A.T. Chronopoulos, Y. Gong, H. Grebel, and S.G. Ziavras, ``Performance Evaluation of a 100-TeraOps Parallel System,'' 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, September 2-4, 1998, pp. 204-211.

·         X. Li, S.G. Ziavras, and C.N. Manikopoulos, ``Parallel Generation of Adaptive Multiresolution Structures for Image Processing,'' Concurrency: Practice and Experience, Vol. 9, No. 4, April 1997, pp. 241-254.

·         S.G. Ziavras and A. Mukherjee, ``Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduced Hypercube Parallel Computers,'' Parallel Computing, Vol. 22, 1996, pp. 595-606.

·         X. Li, S.G. Ziavras, and C.N. Manikopoulos, ``Parallel DSP Algorithms on TurboNet: An Experimental Hybrid Message-Passing/Shared-Memory Architecture,'' Concurrency: Practice and Experience, Vol. 8, No. 5, June 1996, pp. 387-411.

·         S.G. Ziavras and M.A. Sideras, ``Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers,'' Parallel Image Analysis, Theory and Applications, L.S. Davis, K. Inoue, M. Nivat, A. Rosenfeld, and P.S.P. Wang (Eds.), World Scientific, 1996, pp. 23-42.

·         S.G. Ziavras, H. Grebel, and A. Chronopoulos, ``A Low-Complexity Parallel System for Gracious, Scalable Performance. Case Study for Near PetaFLOPS Computing,'' PetaFLOPS Computing/Point Design Studies, 6th Symposium on the Frontiers of Massively Parallel Computation, Special Session on the NSF/DARPA/NASA-funded New Millennium Computing Point Designs, Annapolis, Maryland, Oct. 27-31, 1996, pp. 363-370.

·         S.G. Ziavras, ``Performance Analysis for an Important Class of Parallel Processing Networks,'' International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'96), Beijing, China, June 12-14, 1996, pp. 500-506.

·         S.G. Ziavras, H. Grebel, and A.T. Chronopoulos, ``A Scalable/Feasible Parallel Computer Implementing Electronic and Optical Interconnections for 156 TeraOPS Minimum Performance,'' PetaFLOPS Architecture Workshop organized for the NSF/DARPA/NASA-funded Point Designs, Oxnard, California, April 22-25, 1996, pp. 235-266.

·         S.G. Ziavras, ``Scalable Multifolded Hypercubes for Versatile Parallel Computers,'' Parallel Processing Letters, Vol. 5, No. 2, June 1995, pp. 241-250.

·         S.G. Ziavras, ``Generalized Reduced Hypercube (GRH) Interconnection Networks for Massively Parallel Computers,'' Networks for Parallel Computations, D.F. Hsu, A. Rosenberg, and D. Sotteau (Eds.), American Mathematical Society, 1995, pp. 307-325.

·         S.G. Ziavras, ``RH: A Versatile Family of Reduced Hypercube Interconnection Networks,'' IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 11, Nov. 1994, pp. 1210-1220.

·         S.G. Ziavras and N.G. Haravu, "Processor Allocation Strategies for Modified Hypercubes," IEE Proceedings E: Computers and Digital Techniques, May 1994, pp. 196-204.

·         S.G. Ziavras and M. Khatri, ``Binary Trees of Modified Hypercubes: A Family of Networks for Hypercube-Like Parallel Computers,'' International Journal of Electronics, Vol. 76, No. 1, Jan. 1994, pp. 27-36.

·         S.G. Ziavras, ``A Class of Scalable Architectures for High-Performance, Cost-Effective Parallel Computing,'' 6th IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, Oct. 26-29, 1994, pp. 162-169.

·         S.G. Ziavras, ``On the Problem of Expanding Hypercube-Based Systems,'' Journal of Parallel and Distributed Computing, Vol. 16, No. 1, Sept. 1992, pp. 41-53.

 

4.     UBIQUITOUS COMPUTING

USER PRIVACY

COMPUTER AND NETWORK SECURITY

·         K.M. Salehin, R. Rojas-Cessa, and S.G. Ziavras, "A Method to Measure Packet Processing Time of Hosts using High-Speed Transmission Lines," IEEE Systems Journal, Vol. 9, No. 4, Dec. 2015, pp. 1248-1251.

·         S. Motahari, S. Ziavras and Q. Jones, "Online Anonymity Protection in Computer-Mediated Communication,” IEEE Transactions on Information Forensics & Security, Vol. 5, No. 3, September 2010, pp. 570-580.

·         N.B. Guinde and S.G. Ziavras, “Efficient Hardware Support for Pattern Matching in Network Intrusion Detection,” Computers and Security (The official journal of Technical Committee 11 (computer security) of the International Federation of Information Processing), 2010.

·         N.B. Guinde and S.G. Ziavras, “Novel FPGA-Based Signature Matching for Deep Packet Inspection,” 4th Workshop in Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices, April 2010.

·         S. Motahari, S. Ziavras and Q. Jones, "Preventing Unwanted Social Inferences with Classification Tree Analysis," 21st IEEE International Conference on Tools with Artificial Intelligence, Newark, New Jersey, November 2-5, 2009, pp. 500-507.

·         S. Motahari, S. Ziavras, M. Naaman, M. Ismail, and Q. Jones, "Social Inference Risk Modeling in Mobile and Social Applications," IEEE International Conference on Privacy, Security, Risk and Trust (PASSAT2009), 2009.

·         S. Motahari, S. Ziavras and Q. Jones, "Designing for Different Levels of Social Inference Risk," 5th ACM Symposium On Usable Privacy and Security (SOUPS), Mountain View, California, July 15-17, 2009.

·         S. Motahari, S. Ziavras, R.P. Schuler and Q. Jones, “Identity Inference as a Privacy Risk in Computer-Mediated Communication,” 42nd Hawaii International Conference on System Sciences, Waikoloa, Big Island, Hawaii, Jan. 5-8, 2009.

·         N. Guinde and S.G. Ziavras, “An Adaptable Platform for Network Intrusion Detection Systems,” 8th New Jersey Universities Homeland Security Research Consortium Symposium  on Homeland Security, Princeton University, New Jersey, Dec. 5, 2008 (poster).

 

5.     IMAGE PROCESSING & REAL-TIME FACE RECOGNITION

COMPUTER VISION, etc.

·         I. Sajid, S.G. Ziavras and M.M. Ahmed, “Efficient Face Recognition using Frequency Distribution Graph Matching,” IET Image Processing, Vol. 6, No. 8, August 2012, pp. 1161–1169.

·         I. Sajid, S.G. Ziavras and M.M Ahmed, “Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance,” 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, September 2010.

·         I. Sajid, S.G. Ziavras and M.M. Ahmed, “FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization,” International Conference on Computer Vision Theory and Applications, May 2010.

·         S.G. Ziavras and M.A. Sideras, ``Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers,'' International Journal of Pattern Recognition and Artificial Intelligence, Special Issue on Parallel Image Analysis, Theory and Applications, Vol. 9, No. 4, August 1995, pp. 679-698.

·         S.G. Ziavras and P. Meer, ``Adaptive Multiresolution Structures for Image Processing on Parallel Computers,'' Journal of Parallel and Distributed Computing, Vol. 23, No. 3, Dec. 1994, pp. 475-483.

·         S.G. Ziavras and D.P. Shah, ``Efficient Implementation of Multilevel Algorithms on Hypercube Supercomputers for Computer Vision,'' Workshop on Computer Architectures for Machine Perception '93 (CAMP'93), New Orleans, Louisiana, Dec. 15-17, 1993, pp. 313-322.

·         S.G. Ziavras, ``Efficient Mapping Algorithms for a Class of Hierarchical Systems,'' IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 11, Nov. 1993, pp. 1230-1245.

·         S.G. Ziavras and M.A. Siddiqui, ``Pyramid Mappings onto Hypercubes for Computer Vision: Connection Machine Comparative Study,'' Concurrency: Practice and Experience, Vol. 5, No. 6, Sept. 1993, pp. 471-489.

·         S.G. Ziavras, ``Embedding Multilevel Structures into Massively Parallel Hypercubes - Connection Machine Results for Computer Vision Algorithms,'' 4th Symposium on the Frontiers of Massively Parallel Computation, McLean, Virginia, Oct. 19-21, 1992, pp. 586-589.

·         S.G. Ziavras, ``Connection Machine Results for Pyramid Computations,'' Supercomputing Symposium '92, Montreal, Canada, June 7-10, 1992, pp. 296-316.

·         S.G. Ziavras and N.A. Alexandridis, ``Improved Algorithms for Translation of Pictures Represented by Leaf Codes,'' Image and Vision Computing, Vol. 6, No. 1, Febr. 1988, pp. 13-20.

·         S.G. Ziavras and N.A. Alexandridis, "Multigranularity Hierarchical Image Transform Architecture," 3rd International Conference on Supercomputing, Boston, Massachusetts, 1988, pp. 118-127.

·         N.A. Alexandridis and S.G. Ziavras, "Object-Quadtrees: An Efficient Structure for Processing/Transmitting Digital Images," International Conference on Digital Signal Processing, Florence, Italy, 1987.

·         N.A. Alexandridis, S.G. Ziavras and P.D. Tsanakas, "Efficient Transmission of Hierarchically Structured Images Using the Walsh Hadamard Transform and Dataflow Architectures," International Conference on Communication Technology, Nov.1987.

·         N.A. Alexandridis, S.G. Ziavras and P. Tsanakas, "Architectural Adaptations for Hierarchical Image Processing/Transmission," IEEE International Conference on Communications, Toronto, Canada, June 22-25, 1986, pp. 424-428.

·         N.A. Alexandridis, N.A. Bilalis and S. Ziavras, "Improved Object Boundary Representation by Investigating Neighbor Quadrants in a  Quadtree Structure of an Image," Digital Techniques in Simulation, Communication and Control, Elsevier Science,  1985, pp. 195-201.

 

 



 

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If you have any comments or questions, please send them to ziavras@njit.edu