Dr. Sotirios G. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens (NTUA), Greece, the M.Sc. degree in Electrical and Computer Engineering from Ohio University, and the D.Sc. degree in Computer Science from George Washington University. He graduated from NTUA in 9 semesters (normal duration of studies: 5 years/10 semesters).
He was a Graduate Teaching Assistant and a Research Assistant at Ohio University, and a Distinguished Graduate Teaching Assistant and a Research Assistant at George Washington University. He received an award in 1984 from the IKY Hellenic State Scholarships Foundation for his academic record at the NTUA and the Richard E. Merwin Ph.D. Fellowship in 1986. From 1988 to 1989, he was also with the Computer Vision Laboratory of the Center for Automation Research at the University of Maryland in College Park, performing research in supercomputing techniques for parallel computer vision and numerical analysis (actual implementations on a Connection Machine supercomputer were also involved). He was with the RISO National Research Laboratory of Denmark in the summer of 1983, performing research in interactive computer graphics. He was a visiting Professor in the Electrical and Computer Engineering Department at George Mason University in the Spring of 1990. He joined the Electrical and Computer Engineering Department at NJIT in the Fall of 1990 as an Assistant Professor. He was promoted to Associate Professor in 1995 and then to Professor in 2001. He also holds a joint appointment in Computer Science.
He is currently the Vice Provost for Graduate Studies and Dean of the Graduate Faculty at NJIT.
He served as the Associate Chair for Graduate Studies in the ECE Department from 2001 to 2004 and again from 2007 to 2008. He is the recipient in 2011 of the NJIT award in the category Excellence in Graduate Instruction.
He has authored about 200 papers. He is the Director of the Computer Architecture and Parallel Processing Laboratory (CAPPL). His main research interests are advanced computer architecture, reconfigurable computing, chip multiprocessors, parallel processing (architectures and algorithms), embedded systems, special-purpose hardware designs (for image processing, numerical analysis, etc.), hardware support for network security and ubiquitous computing.
He received a Research Initiation Award from the National Science Foundation in 1991. His research has been supported by the National Science Foundation (NSF), the Defense Advanced Research Projects Agency (DARPA), the New Jersey Commission on Science and Technology (NJCST), the U.S. Department of Energy (DOE), AT&T, NJIT, etc. He received in 1996 an NSF/DARPA (also sponsored by NASA) New Millennium Computing Point-Design Studies grant (findings) for the early design and feasibility analysis of a supercomputer that could achieve by the year 2005 near PetaFLOPS performance; only eight point-design projects were funded nationwide and the first general-purpose supercomputer to yield 1 PetaFLOPS performance was 12 years away (the IBM Roadrunner in May 2008). He has served as a reviewer for many NASA and NSF proposals, and as a panel member for the evaluation of research proposals submitted to Federal Government agencies.
He has served as a program committee member for many international conferences. He has presented about 40 invited seminars/talks at universities and scientific workshops.
Among many recent CAPPL Laboratory innovations, his CAPPL research group introduced:
· The concept of end-user programmable semi-customized multicores for high-performance embedded computing using FPGAs (in 2002).
· The concept of vector coprocessor sharing for multicores embedded in FPGAs (in 2005).
· Various runtime policies for vector coprocessor sharing in general-purpose multicores in order to maximize the performance while also minimizing the overall energy consumption (static and dynamic energy); this work was benchmarked using FPGA-based prototypes as well as ASIC (Application-Specific Integrated Circuit) implementations (in 2010).
· The first known implementation of LU (Lower-Upper triangular) factorization on FPGAs using floating-point units (in 2003). LU factorization is of paramount importance to scientific and high-performance computing. Our approach for huge sparse matrices has since been also used by the EDA (Electronic Design Automation) industry to speedup circuit simulation.
· Parallel solution of Newton’s power-flow equations on multiprocessors embedded in FPGAs in an effort to facilitate real-time monitoring of the Power Grid (in 2006).
· FPGA-based network intrusion detection involving real-time pattern matching that also facilitates (the concept of) efficient runtime pattern updates (in 2009).
· Dynamic/runtime resource and energy management for reconfigurable mixed-mode (i.e., simultaneously supporting the SIMD and MIMD parallel execution modes) multiprocessors embedded in FPGAs (in 2005).
He has served as an Associate Editor or Editor for such journals as Pattern Recognition, and has been listed in many biographical publications such as Marquis: Who's Who in Science and Engineering; Who's Who in America; Who's Who in the World; Who's Who in the East; Who's Who in American Education; Who's Who in Engineering Education.
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