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ECE495 Computer Engineering Design Laboratory

Appendix 5.1

VHDL code for exp5_alu

-- CoE 485 Exp. 5

--  8-bit ALU

--  Dr. Hou

--

--  result <= a + b,   if op = 0

--         <= a and b, if op = 1

--

library ieee;

use ieee.std_logic_1164.all;

library lpm;

use lpm.lpm_components.all;

entity exp5_alu is

port (a, b: in std_logic_vector(7 downto 0);

      op: in std_logic_vector(0 downto 0);

      result: out std_logic_vector(7 downto 0));

end exp5_alu;

architecture structural of exp5_alu is

signal add_result, and_result: std_logic_vector(7 downto 0);

signal mux_data: std_logic_2D(1 downto 0, 7 downto 0);

begin

  alu_adder: lpm_add_sub

      generic map (lpm_width=>8)

      port map (dataa=>a, datab=>b, result=>add_result);

  and_result <= a and b;

  for_label: for i in 7 downto 0 generate

      mux_data(0,i) <= add_result(i);

      mux_data(1,i) <= and_result(i);

  end generate;

  alu_mux: lpm_mux

      generic map (lpm_width=>8, lpm_size=>2, lpm_widths=>1)

      port map (data=>mux_data, result=>result, sel=>op);

end structural;

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