NJIT - COE485 Experiment 2 - Introduction to Microsequencer Design

The objective of this experiment is to learn the basic operating principles of microsequencers.

John D. Carpinelli, Computer Systems Organization & Architecture, Addison Wesley.

The control unit is responsible for coordinating actions within the CPU. The control unit decodes the instruction and issue a set of control signals that result in the instruction’s execution. These control signals cause data to be routed correctly within the CPU, generate correct external control signals, such as RD and WR in the 8085, and cause the ALU to perform the correct operation on the data.

There are two methods used to generate these control signals. Hardwired control units implement the control signals using combinational logic. The inputs to this control logic are generated by the control unit and also taken from the instruction opcode. Microprogrammed control units, or microsequencers, are another approach. In this method, control signals are the output of the control memory, the control unit generates the control signals by stepping through the correct

sequence of control memory locations. Each word of control memory is called a microinstruction. The sequence is initiated based on the instruction to be executed; the next microinstruction is generated from the current microinstruction and external conditions.

The general configuration is shown in Figure 2.1. The sequence of operations is as follows:

1. The address of the next microinstruction to be executed is loaded into the address register. This becomes the input address to the control memory.

2. The control memory decodes its input address and puts out the microinstruction. This microinstruction has two functions. First, it makes available the control signals to sequence execution of the instruction. Note that the microsequencer does not actually execute the instruction; it generates control signals which cause other hardware within the CPU (such as the ALU) to execute the instruction. Second, it generates address and condition signals.

3. Based on the condition signals, the multiplexer generates the address of the next microinstruction. Possible next addresses are discussed later in this experiment.

The address multiplexer is used to select one out of a number of possible addresses for the next microinstruction to be executed. There are four standard possibilities.

INCR The next address in control memory. This is often used to execute a series of microinstructions that occupy consecutive locations in control memory.

ADDR The address specified by control memory. This is used to specify jumps within control memory. This is typically used to jump to the opcode fetch routine when finished executing the instruction. It is also combined with INCR to perform conditional jumps within the microcode, i.e. if the jump is taken, the next microinstruction address is taken from ADDR, otherwise it is taken from INCR.

SBR The address stored in the microsubroutine register. Just as high-level and assembly language programs may have subroutines which can be invoked from different locations within the program, microcode may also use microsubroutines. These microsubroutines usually perform functions, such as indirect addressing, that are common to many instructions. The microsubroutine register contains the return address of the microsubroutine. The register is loaded when a microcall is executed and is read when a microreturn is reached. If nested micro-subroutines are used in the system, the register must be replaced with a hardware stack.

MAP The address based on the instruction to be executed. The mapping logic reads the opcode of the instruction to be executed and generates the microaddress of the first microinstruction used to execute the instruction. The logic used to generate the output depends on the placement of microcode within the control memory. The address to be used is determined by the branch logic. This is combinatorial logic that selects the next address based on the current microinstruction and external status bits. The branch logic also generates the signal used to load SBR.

In the first part of this experiment, INCR and SBR are not used; only ADDR and MAP supply the next microaddress. Furthermore, all branches are unconditional, so the branch logic defaults to a single control signal derived from the control memory.

In the second part, SBR is added as a possible source for the next address. When designing the additional hardware to incorporate SBR, keep in mind that the next address must still be generated in only one clock cycle. This can be accomplished by using multiplexers without latched outputs, by using master-slave clocking signals on the multiplexers, or any other method you choose.

This is a single register which holds the address of the microinstruction. The clock used to load the register is actually the system clock. In this experiment, the register is incorporated within the multiplexer chip. Instead of the oscillator normally used as the system clock, you will use a DEBOUNCED push button switch to allow you to single step through the microcode.

The control memory is typically a small ROM. For this experiment, you will use a 2816 EEPROM. You will enter the microcode using the DC assembler directive. Ground all unused address lines.

For this experiment, two additional pieces of hardware are needed. The instruction register, which normally holds the opcode for input to the mapping logic, will be replaced by two DIP switches. This is done to simplify hardware and facilitate debugging. Also, three LEDs with current-limiting resistors will be connected to signals Z₁, Z₂ and Z₃ of the control memory. Since this experiment does not actually use the other components of the CPU, the LEDs will be used to monitor the control signals. Note that all LEDs must be driven by active low logic.

All eight outputs of the control memory are used in this experiment. The format is as follows.

Bit	Function
D₇	Address Multiplexer Control
	0 = Address from EPROM, l = Address from MAP
D₆	Control for LED Z₁, active low
D₅	Control for LED Z₂, active low
D₄	Control for LED Z₃, active low
D_3-0	Address from EEPROM, ADDR

There are three instructions this control unit can execute. They are summarized below.

Instruction	Opcode	LEDs lit during
		T₁	T₂	T₃	T₄
I₁	01	Z₂	Z₃	Z₁	Z₁, Z₂, Z₃
I₂	10	Z₁, Z₃	Z₁, Z₂	Z₂, Z₃	Z₁, Z₂, Z₃
I₃	11	Z₁, Z₂, Z₃	Z₁, Z₂	Z₁	None

A fourth microroutine is needed to implement the opcode fetch. This takes four microinstructions. The first three microinstructions would normally sequence the fetching of the opcode from memory; since this is not done here, use null code to step through these microcode locations. The fourth microinstruction must map to the correct microroutine. All LEDs must be off during the opcode fetch. If the opcode fetch reads an opcode of 00, the microcode should map back to the opcode fetch routine.

1. Design the microcode layout, i.e. which instructions reside in which EPROM locations.

3. Based on the microcode specifications given in this experiment and the microcode layout, write the microcode.

4. Prepare a separate design which has only two instructions, I₁ and I₂ from the previous example. Each instruction should call a microsubroutine at the end of T₃; this microsubroutine is identical to T₃. The design should include the microcode and the hardware necessary to implement the microsubroutine register. Note that one additional address selection bit is required. In order to keep the design to eight bits, do not include output Z_l in this design. Just as opcode 00 branches back to the opcode fetch routine, opcode 11 should also branch back to the opcode fetch.

2. Wire and test the circuit. Use the debounced push button switch for the system clock, and the toggle switches for the instruction register.