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COE485 Computer Engineering Design Laboratory
Experiment 5
Microcoded CPU Design
The objective of this experiment is to design and implement a microcoded CPU using the ALTERA EPM series high-density programmable logic devices.
Review Chapter 7 of Computer Systems Organization & Architecture by John Carpinelli.
One 2816 EEPROM or equivalent to serve as system memory
One 2114 RAM or equivalent to serve as system memory
In this experiment, the student will design a microcoded CPU based on the ALTERA EPM7128S PLD. A VHDL will be develop based on the CPU design.
The CPU must meet the following specifications.
The CPU must be able to access 256 4-bit words of memory. This implies that an 8-bit Address Register (AR) and an 8-bit Program Counter (PC) are needed.
The CPU must be able to access the 4-bit memory via a 4-bit Data Register (DR).
The CPU must have two internal4-bit registers: the accumulator (AC) and a general-purpose register (R).
The CPU must have a 1-bit condition flip-flop (Z), which derives its input as described below.
The CPU must be capable of executing the instructions shown in Table 5.1, excluding the instructions shown in italics. (These are the extra credit instructions described below.) In your design, make these instruction codes perform NOPs. Note that V is defined as the logical OR of the bits of Ai; this is similar in function to a zero flag. Also note that LOAD, LOADSP, STORE and JUMP use 8-bit addresses (G) as part of the opcode. These are 3-"half-byte" instructions; the others use only one half-byte each. The address is stored as the low order four bits first, followed by the high order four bits.
Extra credit: Implement the LOADSP, PUSH and POP instructions, along with the 8-bit stack pointer (SP) used by these instructions.
In addition to the CPU design, your system must include program memory. Configure the EEPROM as locations 00H- 7FH and the RAM as locations 80H-FFH in your design.
| Table 5.1: CPU instruction set. | ||
|
Instruction |
Opcode |
Operation |
|
NOP |
000X |
No operation |
|
LOAD |
0010 G |
AC ¬ M[G] |
|
LOADSP |
0011 G |
SP ¬ G |
|
STORE |
010X G |
M[G] ¬ AC |
|
MOVE |
011X |
R ¬ AC |
|
JUMP |
100D G |
If D=0 or (D=1 and Z=1), jump to address G If D=1 and Z=0, execute the next instruction |
|
TEST |
101D |
If D=0 Z ¬ V; If D=0 Z ¬ V’ |
|
ADD |
1100 |
AC ¬ AC + R |
|
AND |
1101 |
AC ¬ AC & R |
|
PUSH |
1110 |
M[--SP] ¬ A |
|
POP |
1111 |
AC ¬ M[SP++] |
1. Prepare a preliminary hardware design for your CPU. Explain the purpose of any temporary registers. Describe how the components communicate with each other and devices outside the CPU.
2. Prepare a preliminarily commented version of the microcode for your system.
3. Prepare a test program which demonstrates that your CPU successfully implements the given instruction set.
4. Prepare a .VEC file with which to simulate your design for the EPM7128S.
5. Prepare a schedule for this project. Include sufficient time to test both the hardware and software.
Build, test, simulate and debug your design until it works.
