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COE485 Computer Engineering Design Laboratory
Experiment 4
Hardwired CPU Design
The objective of this experiment is to design and implement a simple hardwired CPU using the ALTERA EPM series high-density programmable logic devices.
Review Chapter 6 of Computer Systems Organization & Architecture by John Carpinelli.
Equipment Needed
In this experiment, the student will design a hardwired CPU based on the ALTERA EPM 7128S PLD. The EEPROM will be used as both program memory and data memory. A VHDL program will be developed based on the CPU design. The design must fit the EPM 7128S. The content of the accumulator must be displayed on the LEDs of the UP1 board.
The CPU must meet the following specifications. The CPU must be able to access 64 8-bit words of memory. This implies that a 6-bit Address Register (AR) and a 6-bit Program Counter (PC) are needed.
The CPU must be able to access the 8-bit memory via an 8-bit Data Register (DR).
The CPU must have an 8-bit accumulator (AC)
The CPU may include additional internal components, such as an instruction register, depending on each student's design. However, the entire design, including control logic, must fit on a single EPM7128S.
The CPU must be capable of fetching, decoding and executing the instructions shown in Table 4.1. In this table, AAAAAA specifies a 6-bit address.
The CPU must be able to successfully read instructions and data from memory.
Table 4.1:CPU instruction set.
|
Instruction |
Opcode |
Operation |
|
ADD |
00AAAAAA |
AC ¬ AC + M[AAAAAA] |
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AND |
01AAAAAA |
AC ¬ AC & M[AAAAAA] |
|
JMP |
10AAAAAA |
PC ¬ AAAAAA |
|
DEC |
11XXXXXX |
AC ¬ AC - 1 |
1. Prepare a preliminary design for your CPU. Include a commented .VHD file.
2. Prepare a .VEC file to simulate your design.
3. Prepare a test program which, when stored in external memory, demonstrates that your CPU successfully implements the given instruction set.
Build, test, simulate and debug your design until it works.
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