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COE498 Advanced Computer System Design Lab

Chapter 4

EXPERIMENT 4

CPU Design with Support for External Interrupts

4.1   Objective

The objective of this experiment is to design, simulate, and build a microcoded CPU capable of servicing external interrupt requests. Interrupts will be employed to initiate memory-mapped I/O. Firmware in the microcode will implement polling to determine the type of interrupt request.

The CPU design should include several Altera programmable logic devices (PLDs).

 

4.2   What You Need

• Two Protoboards.

• An Altera EPM7064-68 or EPM7096-68 with a DIP adapter for the implementation of the execution unit.

• An Altera EPM7064-68 or EPM7096-68 with a DIP adapter for the implementation of the I/O decode and interrupt unit. Two Altera EPM5064-44s with DIP adapters may be used instead.

• One Altera EPS448-28 for the microcode.

• One 2816 EEPROM or equivalent.

• One 2114 RAM or equivalent.

• Several push buttons, LEDs, and DIP switches for I/O devices and external interrupt requests.

• PC running Altera Max+PLUS II v6 or v7 software and Altera SamPlus.

 

4.3   Introduction

This CPU design is basically a major extension of the design in the last experiment of CoE 485. The system specifications follow:

• The CPU will have three major sections. The execution unit which will contain the ALU, the registers, the 1-bit zero ag (Z), the 8-bit CPU address bus, and the 4-bit CPU data bus; this section can be implemented with an EPM7064 or EPM7096. The microcode unit to produce control signals; this section will involve the EPS448. Finally, the I/O decode and interrupt unit; the implementation of this section may involve an EPM5064 or an EPM7064.
   

• 128 4-bit words of ROM starting at address 0 and 128 4-bit words of RAM starting at address 128 (decimal). This arrangement will require an 8-bit program counter (PC), an 8-bit memory-address register (MAR), a 4-bit memory-data register (MDR), an 8-bit system address bus, and a 4-bit sys- tem data bus.
   

• The CPU should be able to access a minimum of two 4-bit input ports (namely, IP0, IP1, IP2, and IP3) and an output port (OP0). The input and output ports should be implemented with 4xDIP switches and 4xLEDs, respectively. A 4-bit interrupts-pending status register (IPEN) also should be included to denote the type (in this case, ID number) of pending interrupts. Another 4xDIP switch input port can be added to support the optional interrupt D, as described below. External hardware should be used to decode the memory-mapped I/O port address.
   

• The CPU should have a minimumof two program-addressable 4-bit registers: an Accumulator (AC) and a general-purpose Data Register (DR).
   

• The 1-bit zero ag (Z) in the CPU will be set by instructions as shown in Table 4.1.
   

• The CPU should have two interrupt-related modes, corresponding to interrupts enabled and interrupts disabled, respectively. While executing user code, interrupts should be enabled. While servicing an interrupt (i.e., while executing an interrupt service routine - ISR), the CPU should disable itself for the processing of any additional interrupts. Additional interrupts should still be recorded, but not processed until the current interrupt is completely serviced. Interrupts should be enabled at the end of the ISR. Therefore, nested interrupts will not be allowed.
   

• To support interrupts, a 1-bit interrupt-request ag (IRQ) and a 1-bit interrupt-enable flag (IEN) are needed. Since the interrupts-pending status register (IPEN) is external to the execution unit (EPM7064 or EPM7096), the IRQ and IEN can be controlled by the interrupt hardware (EPM5064 or EPM7064) and the microcode unit (EPS448). The CPU should check for pending interrupts at the end of each instruction cycle. Pending interrupts are never serviced by CPUs before complete execution of the current instruction; otherwise, the information stored automatically when entering the ISR may not be complete to resume reliable execution of the user program.
   

• When entering the ISR, the CPU should automatically save the user program counter (PC) and the zero ag (Z). The PC and Z ag should be automatically restored when returning from the ISR. The AC and DR must also be saved in the beginning and restored at the end of the ISR.
   

• The CPU instruction set is shown in the upper half of Table 4.1. Note that LOAD, STORE, and JUMPZ are 3-word instructions with a 4-bit opcode and an 8-bit address. NOP, MOVE, SUB, AND, and RETINT are 1-word instructions having just an opcode.

Optional instructions for extra credit are listed in the lower half of Table 4.1. These include 1-word and 2-word instructions. These instructions can be implemented with very little or no additional hardware in the execution unit (EPM7064 or EPM7096).

Hardware to support three or four different interrupts.

The action taken by the ISR depends each time on the type of interrupt. All possible actions are described in Table 4.2.

4.4   Experiment

Pre-Lab Assignment

Design the above CPU in block diagram form. Write the microcode. Design the hardware which is external to the CPU.

 

Lab Assignment

Develop Altera Hardware Description Language (AHDL) code for programming the PLDs and SamPlus code for the EPS448 microcode.

Use the simulator in Max+PLUS II to simulate the CPU for the set of required instructions. For extra credit, your code also should demonstrate the optional features of the CPU.

Demonstrate the simulator and the hardware to the instructor.

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