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The 8251A Programmable Communication Interface

This Intel chip is capable of both synchronous and asynchronous bidirectional serial communication hence it is also referred to as a Universal Synchronous- Asynchronous Receiver Transmitter (USART). Synchronous communication can be used if both ends of the connection agree to certain communication protocols. It is more commonplace to use asynchronous communications using a UART, a Universal Asynchronous Receiver Transmitter so our discussion will be confined to that form of operation.

This UART contains two registers addressed as two ports. One port is the command/status register and the other port is the data register. The UART is initialized by writing to the command register. When this port is read it supplies status information. The data port contains the last byte received as well as  the byte which is to be transmitted.

If the UART is in the reset state then it expects to be initialized first with a single MODE instruction which can then be followed by any number of COMMAND instructions. The bits of the mode instruction, designated

S2,  S1, EP, PEN, L2, L1, B2, B1

have the following interpretation:

1.    S2, S1 = 00 is illegal.

2.    S2, S1 = 01  for 1 stop bit.

3.    S2, S1 = 10  for 1 1/2  stop bits.

4.    S2, S1 = 11  for 2 stop bits.

1.   L2, L1 = 00 for 5 bits.

2.   L2, L1 = 01 for 6 bits.

3.   L2, L1 = 10 for 7 bits.

4.   L2, L1 = 11 for 8 bits.

1.    B2, B1 = 01 for a 1× clock speed.

2.    B2, B1 = 10 for a 16× clock speed.

3.    B2, B1 = 11 for a 64× clock speed.

Any number of COMMAND instructions can follow the MODE instruction.

The bits of the command instruction, designated by 

X, IR, RTS, ER, SBRK, R × E, DTR, T × E 

have the following meaning:

Analysis of the above information leads us to the conclusion that, after reset, sending a 4EH MODE byte to the control register should initialize the UART for serial transmission with 1 stop bit, no parity, 8-bit format with a 16× clock. This can be followed by a 27H COMMAND word to the control register to enable transmission, reception, and to pull down the and pins.

Intel suggests that after power is applied one cannot be absolutely sure that the UART is in the reset state before beginning its initialization. It is therefore more prudent to send the bytes 0AAH, 40H, 4EH and 27H. If the chip is in the reset state then 0AAH will be taken as a proper mode instruction and 40H will then be the command instruction telling the UART to enter the reset state. If, on the other hand, the chip is not in a reset state, it will take the 0AAH as a command instruction, which will do no harm, and the subsequent 40H will be taken as a command instruction, causing it to go into the software reset state. After that, the 4EH and 27H do their normal job.

The following simple subroutine can be used for the UART initialization

dreg equ $10000 ; data port
csreg equ $10001 ; control status port
;
serinit lea csreg,a0
; The next 2 lines are to get the UART
; to a reset state in case it has not
; been reset prior to initialization.
         move.b #$aa,(a0)
         move.b #$40,(a0)
; Now that we are sure the UART is reset,
; we proceed with a mode instruction to
; obtain operation with 1 stop bit,
; no parity, 8 data bits and a 16x clock.
         move.b #$4e,(a0)
; COMMAND instruction. RxE = 1 to enable
; reception, TxE = 1 to enable transmission,
; Also make RTS* = 0 and DTR* = 0.
         move.b #$27,(a0)
         rts

When the command register is read it supplies status information. The bits of the status byte are designated by

DSR, SY N DET, FE,OE, PE, T × E, R × RDY, T × RDY

Only the two least significant bits are of interest to us. They are the following:

 

The following short subroutines can be used to communicate with the serial port.

; Use port equates from previous routine
davbit   equ   2      ; receive data available mask
bfebit   equ   1      ; transmit buffer empty mask
;
; Get  a  char,  mask  with 7fH.  Char in D1.B
charin   move.b csreg,d0    ; get status
         andi.b #davbit,d0  ; Mask for char input status
         beq.s charin       ; No char, then loop back
         move.b dreg,d1     ; Get the char
         andi.b #$7f,d1     ; Get rid of bit 7
         rts                ; Char in d1.b
;
; Send a char from D1.B
charout move.b csreg,d0     ; get status
        andi.b #bfebit,d0   ; Mask for buffer empty status
        beq.s charout       ; Not empty, then loop back
        move.b d1,dreg      ; Send the char
        rts                 ; Done

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