NJIT - EE395 - Explanation of the Single Board Computer (SBC) Design

In chapter 11 of Antonakos’s book the author talks about a single board microcomputer designed around an M68000 CPU. That computer is designed to be interfaced to another computer, such as a PC, using a serial port connection. The microcomputer is controlled by a monitor program supplied on the diskette furnished with Antonakos’s book. This is located in the CH11 subdirectory.

The design presented in figure 1 is a modification of the one appearing in chapter 11 of Antonakos’s book. Antonakos’s design has been simplified substantially by moving to an 8-bit CPU. Other changes were made to reduce the amount of wiring required to allow completion of the project in the shortest possible time. As a consequence our monitor had to be modified to account for the change in address decoding and differences in the choice of support chips used in this design. Other changes were made to add additional features that the original monitor didn’t have, such as S-file downloading, disassembling, tracing, and breakpointing. These are important tools for debugging (troubleshooting) programs in their design stages.

Originally an 8-bit 68008 microprocessor was chosen as a substitute for the 16- bit 68000 CPU so thoroughly discussed in Antonakos’s book. The two CPUs were completely software compatible even though the 68008 had only an 8-bit data bus. It was selected in order to minimize the amount of wiring required for the construction of the SBC. With this choice, the number of ROM and RAM chips was cut by a factor of two.

When production of the MC68008 CPU was discontinued, and supplies of the chip started to become exhausted, a change was made to the MC68EC000 CPU. This chip has the ability to be operated in either 8-bit or 16-bit mode.

If the MODE pin on this CPU is grounded when the CPU is reset then the chip wakes up operating in 8-bit mode. Unlike the MC68000, this chip lacks the signals used for interfacing to old M6800 support chips. In particular it lacks the

signal which was also used to inform the CPU that autovectored interrupts were desired. This signal was replaced by the autovectoring signal

In all other respects this chip is identical with the MC68000 CPU.

When the MC68EC000 is operated in 8-bit mode, the

signal is of no consequence, but

is used to inform the peripheral chips that valid data is present on the data bus during a write cycle, or to inform the peripherals to put data on the data bus during read cycles. For 8-bit operation, an A0 address pin is provided as well.

The 28C256 electrically erasable programmable read only memory (EEPROM) was chosen for its quick reprogramming capabilities. This is in contrast with an equivalent 27256 EPROM which would need to be erased with a UV light eraser before being reprogrammed. It was also chosen because it has an adequate storage capability for the latest monitor program.

The 62256 static random access memory (RAM) chip stores 32-kbytes and is a reasonable choice for maintaining a stack and any reasonably sized programs which can be downloaded from a personal computer (PC).

The 74LS138 3 to 8-line decoder chip was chosen to give this system a capability of addressing 8 different devices. The decoding used is definitely not unique and all peripheral devices can be found at more than one address.

¿From the schematic diagram it is clear that the 32-kbyte 28C256 EEPROM is enabled with the

output from the decoder. It, therefore, occupies the 8- kbyte address space from 0 - 7FFFH. The 62256 32-kbyte RAM chip is enabled with the

output from the decoder. It is consequently addressable from 8000H - 0FFFFH. Since this decoding is not unique the chip can be accessed at other memory locations as well.

The 8251A PCI chip is selected with the

output from the decoder. It is also connected to the A0 address line, so it is addressable, non-uniquely, as two memory mapped ports at 10000H and 10001H. The 74LS244 input port chip, as well as the 74LS373 output port chip, are selected with the

output from the decoder. It is clear that both ports are non-uniquely mapped into memory location 18000H. There are additional decoder outputs which are reserved for future expansion.

An RS-232 communication interface requires a universal asynchronous receiver transmitter (UART) to transform transmitted data from parallel to serial form and received data from serial to parallel form. For our serial interface we use the fast Intel 8251A (programmable communication interface) PCI. Since that chip is not described in Antonakos’s book, a later chapter of this manual will deal with it in detail.

A UART deals with data using TTL compatible voltages, that is 0 and 5 V. The RS-232 interface requires that the TTL signals be inverted and converted to a bipolar form with voltages ranging from ±3V to ±15. Ordinarily the very popular 1488 and 1489 chips are used for this purpose. Their disadvantage is that they require the use of additional +12V and -12V power supplies. The MAX233A TTL-RS232 interface chip does away with that need in that it generates the +10 and -10 voltages internally.

Most UARTS use a clock signal that is 16 times (16×) the actual bit rate of the RS-232 interface. The I8251A is no exception. In our case the clock signal is provided by dividing the 9.8304MHz oscillator signal using the 74HC4020 ripple counter. The baud rates provided are indicated in the schematic.

There are many different ways to create a parallel port interface. Using a sophisticated parallel port chip, such as the MC68230 or the I8255, produces 24 pins of I/O which can be configured in many different ways. This requires that the instructions for the chip be studied and understood in order to learn what data must be written to the chip’s registers in order to configure it for the desired operation. The alternative is to use unsophisticated ICs and bypass those difficulties entirely.

The 74LS244 is a tri-state octal buffer chip. When its output is enabled, it transfers the data on the input pins, I0-I7, to the data bus which is connected to pins D0-D7. This data is put on the bus when the output enable pins

and

on the 74LS244 chip are pulled down. The signal for this purpose is obtained by ORing the 74LS138 decoder output pin

signal with the

signal.

The 74LS373 octal transparent latch implements an 8-bit output port. The

pin is grounded so that the tri-state output is always enabled. This way any data sent to the output port is permanently available to any peripheral device connected to it. The data that is supplied on the D0-D7 pins is loaded into the 8-bit buffer when the latch enable pin on the 74LS373 is pulled up. The signal for this is supplied by a 74LS14 inverter which gets its input from the 74LS138 decoder output pin

signal which has been ORed with the

signal.

Now that we have discussed the address decoding for all the chips in this system we are ready to summarize it in a table. The table below gives the addresses (non-unique) for the various components of the system.

Decoding Table for this Project
Device	Address range (hex)
EEPROM MONITOR Static RAM Serial Port Data Register Serial Port Control/Status Register \|\| Input Port \|\| Output Port	0000 - 7FFF 8000 - FFFF 10000 10001 18000 18000

There are numerous ways of constructing precision oscillator circuits. When the price, and trouble taken, are considered it is quickly concluded that the simplest thing to do is to use an integrated oscillator. Such an oscillator possesses only three pins. One is used for connecting to +5 V, one for ground and one for the clock output.

The 9.8304MHz oscillator output is used to drive the 68EC000 microprocessor directly. It also serves as the input to the 74HC4020 binary ripple counter to produce a number of lower frequencies. Thus the counter’s Q1 output is used to clock the UART at a slightly slower 4.9152 MHz. The Q4 output produces a frequency of 614,400 kHz. This is 16 times the frequency needed at the T × C and R × C terminals of the UART to get it to communicate at a bit rate of 38.4 kHz. Some other operating frequencies are shown on the SBC schematic.

To reset the CPU it is necessary to pull down the

and

pins for at least 100 ms. The CPU begins to execute initialization routines when these pins are subsequently permitted to rise to 5 volts. A single pole, normally open, momentary switch which is buffered by a 74LS14 Schmitt inverter is used to reset the CPU. The time constant of the RC circuit which is connected to the switch is 330 ms. The output signal of the 74LS14 Schmitt inverter is applied to two 74LS05 open collector inverters. These are used to hold the

and

T pins at low voltage long enough for the power supply voltage to reach 5 volts, thus causing CPU reset on power up.

The

and

pins are bi-directional. It is therefore essential to keep them independent of each other. That is the reason they are connected in the manner shown. Open collector devices have for output a transistor with the collector only connected to the output pin. When the output is in a high state the output transistor is cut off so that the output terminal is effectively connected to an open circuit. The 3.3 k resistor pulls the terminal up to +5 V. If the CPU then decides to output a voltage on either the

or the

pin, it can do so without causing any conflicts. This would not be the case with a conventional inverting gate, for example a 74LS04, which has a totem pole output.

The two 7432 OR gates combine the CPU

data strobe signal and the CPU RD /

signal to generate separate

and

signals. Those signals are used directly as inputs to the 8251A PCI chip. The

signal is used to enable the output of the 28C256 EEPROM.

The 62256 RAM chip has different needs. Its output must be disabled when an attempt is made to write to the chip. A destructive conflict could occur if the RAM chip were to put data on the data pins while an external device were to do it at the same time. Connecting the

signal to the

pin on the 62256 RAM avoids possible conflicts. The

signals of the decoder is connected to the

pin of the RAM and its function is to let this chip know that a memory write is desired.

It is noteworthy that this chip can never be asked to perform a memory read and a memory write simultaneously. The connections are such that the two functions are mutually exclusive.

The

pin must be activated some time after the assertion of the address strobe AS and subsequently deactivated after the negation of

. This pin is read by the CPU one clock cycle after the address strobe

is activated. With a 10Mhz clock it means that it is read 100 ns later. Since all of our peripherals are capable of functioning with a CPU clocked at 10 MHz, the simplest thing to do is to connect the

pin directly to the

signal. This way the

pin is asserted at the same time as the

signal.