As part of our educational work, my students and I have developed several Java applets for simulating computer systems, CPUs, and arithmetic and logic hardware. These applets are available without cost under the terms of the GNU General Public License. You may download the applets from this server, or from the textbook's companion web site by following the Student Resources link to the Simulators section.

Since many browsers have dropped support for or are phasing out support for Java, it is necessary to run the applets using the JDK with NetBeans. Click here for instructions for Windows-based systems, or here for instructions for Macs.

The Very Simple CPU Simulator is an instructional aid for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates a 4-instruction CPU introduced in the textbook Computer Systems Organization and Architecture. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the fetch, decode, and execute cycles of each instruction. Click here to download a ZIP file containing this applet and its help files.

The Relatively Simple CPU Simulator, like the Very Simple CPU Simulator, is also an instructional aid for students studying computer architecture and CPU design. It simulates a 16-instruction CPU introduced in the textbook Computer Systems Organization and Architecture. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the fetch, decode, and execute cycles of each instruction. Click here to download a ZIP file containing this applet and its help files.

The Relatively Simple Computer System Simulator. Unlike the previous two simulators, which simulate the functions that occur within a CPU, this simulator illustrates the functions that occur between components in a simple computer system. The system under simulation consists of the Relatively Simple CPU, memory, and a bidirectional I/O port, for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates a 16-instruction CPU introduced in the textbook Computer Systems Organization and Architecture. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the processing of each instruction. Click here to download a ZIP file containing this applet and its help files.

The Wallace Tree Simulator.

Wallace Trees are combinatorial logic circuits used to multiply binary integers. Constructed using carry-save adders, they are a fast, efficient method to implement multiplication. Since these adders do not propagate carry values between bits, they are faster than parallel adders and can produce multiplication products faster than other multiplication hardware. This applet simulates 4-, 6-, and 8-bit Wallace Tree multipliers, as presented in the textbook Computer Systems Organization and Architecture. Students select the size of the Wallace Tree to be simulated and enter values for the operands to be multiplied. The simulator shows the partial products generated by the Wallace Tree, and the results generated by each carry-save adder in the tree, as well as the final product. Students can also examine the internal organization of the carry-save adders to see how they generate their results within the tree. Click here to download a ZIP file containing this applet and its help files.

The Benes Network Simulator is a simple, rearrangeable multistage interconnection networks used in applications ranging from telephone switching systems to multiprocessor systems to network switches. Because of its recursive structure and its ability to realize any one-to-one connection of its inputs to its outputs, it is an ideal first topic to cover in the network switching portion of a network design course. This applet simulates an 8-input Benes network and its most straightforward routing algorithm, the Looping Algorithm, which sets the switches of the network. Click here to download a ZIP file containing this applet and its help files.

The Programmable Logic Device Simulator. Unlike the previous packages, the PLD simulator is more of a visualization tool than a simulator. After selecting the numbers of inputs and outputs, up to four of each, the simulator displays a generic PLD. The user clicks on the junction points to make and break connections. While doing so, the display is updated to show the boolean function realized by each output of the PLD. Unlike the previous simulators, which are designed for specific, fixed-architectures, this tool is designed to provide a more intuitive understanding of how PLDs in general function. Click here to download a ZIP file containing this applet and its help files.